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[Qemu-devel] [PATCH v2 02/17] target-alpha: Rename floating-point subrou
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From: |
Richard Henderson |
|
Subject: |
[Qemu-devel] [PATCH v2 02/17] target-alpha: Rename floating-point subroutines |
|
Date: |
Tue, 12 May 2015 10:39:32 -0700 |
... to match the instructions, which have no leading "f".
Signed-off-by: Richard Henderson <address@hidden>
---
target-alpha/fpu_helper.c | 2 +-
target-alpha/helper.h | 2 +-
target-alpha/translate.c | 68 +++++++++++++++++++++++------------------------
3 files changed, 36 insertions(+), 36 deletions(-)
diff --git a/target-alpha/fpu_helper.c b/target-alpha/fpu_helper.c
index 8acd460..119559a 100644
--- a/target-alpha/fpu_helper.c
+++ b/target-alpha/fpu_helper.c
@@ -493,7 +493,7 @@ uint64_t helper_cvtqt(CPUAlphaState *env, uint64_t a)
return float64_to_t(fr);
}
-void helper_fcvtql_v_input(CPUAlphaState *env, uint64_t val)
+void helper_cvtql_v_input(CPUAlphaState *env, uint64_t val)
{
if (val != (int32_t)val) {
arith_excp(env, GETPC(), EXC_M_IOV, 0);
diff --git a/target-alpha/helper.h b/target-alpha/helper.h
index a451cfe..424ea49 100644
--- a/target-alpha/helper.h
+++ b/target-alpha/helper.h
@@ -94,7 +94,7 @@ DEF_HELPER_FLAGS_3(fp_exc_raise_s, TCG_CALL_NO_WG, void, env,
i32, i32)
DEF_HELPER_FLAGS_2(ieee_input, TCG_CALL_NO_WG, void, env, i64)
DEF_HELPER_FLAGS_2(ieee_input_cmp, TCG_CALL_NO_WG, void, env, i64)
-DEF_HELPER_FLAGS_2(fcvtql_v_input, TCG_CALL_NO_WG, void, env, i64)
+DEF_HELPER_FLAGS_2(cvtql_v_input, TCG_CALL_NO_WG, void, env, i64)
#if !defined (CONFIG_USER_ONLY)
DEF_HELPER_2(hw_ret, void, env, i64)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index efeeb05..b3c5dca 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -718,7 +718,7 @@ static inline void gen_fp_exc_raise(int rc, int fn11)
gen_fp_exc_raise_ignore(rc, fn11, fn11 & QUAL_I ? 0 : float_flag_inexact);
}
-static void gen_fcvtlq(TCGv vc, TCGv vb)
+static void gen_cvtlq(TCGv vc, TCGv vb)
{
TCGv tmp = tcg_temp_new();
@@ -733,7 +733,7 @@ static void gen_fcvtlq(TCGv vc, TCGv vb)
tcg_temp_free(tmp);
}
-static void gen_fcvtql(TCGv vc, TCGv vb)
+static void gen_cvtql(TCGv vc, TCGv vb)
{
TCGv tmp = tcg_temp_new();
@@ -763,8 +763,8 @@ static void gen_ieee_arith2(DisasContext *ctx,
}
#define IEEE_ARITH2(name) \
-static inline void glue(gen_f, name)(DisasContext *ctx, \
- int rb, int rc, int fn11) \
+static inline void glue(gen_, name)(DisasContext *ctx, \
+ int rb, int rc, int fn11) \
{ \
gen_ieee_arith2(ctx, gen_helper_##name, rb, rc, fn11); \
}
@@ -773,7 +773,7 @@ IEEE_ARITH2(sqrtt)
IEEE_ARITH2(cvtst)
IEEE_ARITH2(cvtts)
-static void gen_fcvttq(DisasContext *ctx, int rb, int rc, int fn11)
+static void gen_cvttq(DisasContext *ctx, int rb, int rc, int fn11)
{
TCGv vb, vc;
int ignore = 0;
@@ -830,8 +830,8 @@ static void gen_ieee_intcvt(DisasContext *ctx,
}
#define IEEE_INTCVT(name) \
-static inline void glue(gen_f, name)(DisasContext *ctx, \
- int rb, int rc, int fn11) \
+static inline void glue(gen_, name)(DisasContext *ctx, \
+ int rb, int rc, int fn11) \
{ \
gen_ieee_intcvt(ctx, gen_helper_##name, rb, rc, fn11); \
}
@@ -875,8 +875,8 @@ static void gen_ieee_arith3(DisasContext *ctx,
}
#define IEEE_ARITH3(name) \
-static inline void glue(gen_f, name)(DisasContext *ctx, \
- int ra, int rb, int rc, int fn11) \
+static inline void glue(gen_, name)(DisasContext *ctx, \
+ int ra, int rb, int rc, int fn11) \
{ \
gen_ieee_arith3(ctx, gen_helper_##name, ra, rb, rc, fn11); \
}
@@ -906,8 +906,8 @@ static void gen_ieee_compare(DisasContext *ctx,
}
#define IEEE_CMP3(name) \
-static inline void glue(gen_f, name)(DisasContext *ctx, \
- int ra, int rb, int rc, int fn11) \
+static inline void glue(gen_, name)(DisasContext *ctx, \
+ int ra, int rb, int rc, int fn11) \
{ \
gen_ieee_compare(ctx, gen_helper_##name, ra, rb, rc, fn11); \
}
@@ -1958,7 +1958,7 @@ static ExitStatus translate_one(DisasContext *ctx,
uint32_t insn)
case 0x0B:
/* SQRTS */
REQUIRE_REG_31(ra);
- gen_fsqrts(ctx, rb, rc, fn11);
+ gen_sqrts(ctx, rb, rc, fn11);
break;
case 0x14:
/* ITOFF */
@@ -1984,7 +1984,7 @@ static ExitStatus translate_one(DisasContext *ctx,
uint32_t insn)
case 0x02B:
/* SQRTT */
REQUIRE_REG_31(ra);
- gen_fsqrtt(ctx, rb, rc, fn11);
+ gen_sqrtt(ctx, rb, rc, fn11);
break;
default:
goto invalid_opc;
@@ -2080,76 +2080,76 @@ static ExitStatus translate_one(DisasContext *ctx,
uint32_t insn)
switch (fpfn) { /* fn11 & 0x3F */
case 0x00:
/* ADDS */
- gen_fadds(ctx, ra, rb, rc, fn11);
+ gen_adds(ctx, ra, rb, rc, fn11);
break;
case 0x01:
/* SUBS */
- gen_fsubs(ctx, ra, rb, rc, fn11);
+ gen_subs(ctx, ra, rb, rc, fn11);
break;
case 0x02:
/* MULS */
- gen_fmuls(ctx, ra, rb, rc, fn11);
+ gen_muls(ctx, ra, rb, rc, fn11);
break;
case 0x03:
/* DIVS */
- gen_fdivs(ctx, ra, rb, rc, fn11);
+ gen_divs(ctx, ra, rb, rc, fn11);
break;
case 0x20:
/* ADDT */
- gen_faddt(ctx, ra, rb, rc, fn11);
+ gen_addt(ctx, ra, rb, rc, fn11);
break;
case 0x21:
/* SUBT */
- gen_fsubt(ctx, ra, rb, rc, fn11);
+ gen_subt(ctx, ra, rb, rc, fn11);
break;
case 0x22:
/* MULT */
- gen_fmult(ctx, ra, rb, rc, fn11);
+ gen_mult(ctx, ra, rb, rc, fn11);
break;
case 0x23:
/* DIVT */
- gen_fdivt(ctx, ra, rb, rc, fn11);
+ gen_divt(ctx, ra, rb, rc, fn11);
break;
case 0x24:
/* CMPTUN */
- gen_fcmptun(ctx, ra, rb, rc, fn11);
+ gen_cmptun(ctx, ra, rb, rc, fn11);
break;
case 0x25:
/* CMPTEQ */
- gen_fcmpteq(ctx, ra, rb, rc, fn11);
+ gen_cmpteq(ctx, ra, rb, rc, fn11);
break;
case 0x26:
/* CMPTLT */
- gen_fcmptlt(ctx, ra, rb, rc, fn11);
+ gen_cmptlt(ctx, ra, rb, rc, fn11);
break;
case 0x27:
/* CMPTLE */
- gen_fcmptle(ctx, ra, rb, rc, fn11);
+ gen_cmptle(ctx, ra, rb, rc, fn11);
break;
case 0x2C:
REQUIRE_REG_31(ra);
if (fn11 == 0x2AC || fn11 == 0x6AC) {
/* CVTST */
- gen_fcvtst(ctx, rb, rc, fn11);
+ gen_cvtst(ctx, rb, rc, fn11);
} else {
/* CVTTS */
- gen_fcvtts(ctx, rb, rc, fn11);
+ gen_cvtts(ctx, rb, rc, fn11);
}
break;
case 0x2F:
/* CVTTQ */
REQUIRE_REG_31(ra);
- gen_fcvttq(ctx, rb, rc, fn11);
+ gen_cvttq(ctx, rb, rc, fn11);
break;
case 0x3C:
/* CVTQS */
REQUIRE_REG_31(ra);
- gen_fcvtqs(ctx, rb, rc, fn11);
+ gen_cvtqs(ctx, rb, rc, fn11);
break;
case 0x3E:
/* CVTQT */
REQUIRE_REG_31(ra);
- gen_fcvtqt(ctx, rb, rc, fn11);
+ gen_cvtqt(ctx, rb, rc, fn11);
break;
default:
goto invalid_opc;
@@ -2163,7 +2163,7 @@ static ExitStatus translate_one(DisasContext *ctx,
uint32_t insn)
REQUIRE_REG_31(ra);
vc = dest_fpr(ctx, rc);
vb = load_fpr(ctx, rb);
- gen_fcvtlq(vc, vb);
+ gen_cvtlq(vc, vb);
break;
case 0x020:
/* CPYS */
@@ -2234,7 +2234,7 @@ static ExitStatus translate_one(DisasContext *ctx,
uint32_t insn)
REQUIRE_REG_31(ra);
vc = dest_fpr(ctx, rc);
vb = load_fpr(ctx, rb);
- gen_fcvtql(vc, vb);
+ gen_cvtql(vc, vb);
break;
case 0x130:
/* CVTQL/V */
@@ -2246,8 +2246,8 @@ static ExitStatus translate_one(DisasContext *ctx,
uint32_t insn)
valid instruction merely for completeness in the ISA. */
vc = dest_fpr(ctx, rc);
vb = load_fpr(ctx, rb);
- gen_helper_fcvtql_v_input(cpu_env, vb);
- gen_fcvtql(vc, vb);
+ gen_helper_cvtql_v_input(cpu_env, vb);
+ gen_cvtql(vc, vb);
break;
default:
goto invalid_opc;
--
2.1.0
- [Qemu-devel] [PATCH v2 00/17] target-alpha fpu improvments, Richard Henderson, 2015/05/12
- [Qemu-devel] [PATCH v2 02/17] target-alpha: Rename floating-point subroutines,
Richard Henderson <=
- [Qemu-devel] [PATCH v2 04/17] target-alpha: Set PC correctly for floating-point exceptions, Richard Henderson, 2015/05/12
- [Qemu-devel] [PATCH v2 01/17] target-alpha: Move VAX helpers to a new file, Richard Henderson, 2015/05/12
- [Qemu-devel] [PATCH v2 05/17] target-alpha: Tidy FPCR representation, Richard Henderson, 2015/05/12
- [Qemu-devel] [PATCH v2 06/17] target-alpha: Set fpcr_exc_status even for disabled exceptions, Richard Henderson, 2015/05/12
- [Qemu-devel] [PATCH v2 03/17] target-alpha: Forget installed round mode after MT_FPCR, Richard Henderson, 2015/05/12
- [Qemu-devel] [PATCH v2 07/17] target-alpha: Set EXC_M_SWC for exceptions from /S insns, Richard Henderson, 2015/05/12
- [Qemu-devel] [PATCH v2 09/17] target-alpha: Fix cvttq vs large integers, Richard Henderson, 2015/05/12
- [Qemu-devel] [PATCH v2 08/17] target-alpha: Raise IOV from CVTTQ, Richard Henderson, 2015/05/12
- [Qemu-devel] [PATCH v2 11/17] target-alpha: Fix integer overflow checking insns, Richard Henderson, 2015/05/12
- [Qemu-devel] [PATCH v2 12/17] target-alpha: Implement WH64EN, Richard Henderson, 2015/05/12