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[Qemu-devel] [PATCH 14/31] hw/i386: add a separate region that tracks th
From: |
Paolo Bonzini |
Subject: |
[Qemu-devel] [PATCH 14/31] hw/i386: add a separate region that tracks the SMRAME bit |
Date: |
Mon, 11 May 2015 15:49:00 +0200 |
This region is exported at /machine/smram. It is "empty" if
SMRAME=0 and points to SMRAM if SMRAME=1. The CPU will
enable/disable it as it enters or exits SMRAM.
Signed-off-by: Paolo Bonzini <address@hidden>
---
hw/pci-host/piix.c | 15 +++++++++++++++
hw/pci-host/q35.c | 15 ++++++++++++++-
include/hw/pci-host/q35.h | 1 +
3 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 723836f..a280d57 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -105,6 +105,7 @@ struct PCII440FXState {
MemoryRegion *ram_memory;
PAMMemoryRegion pam_regions[13];
MemoryRegion smram_region;
+ MemoryRegion smram, low_smram;
uint8_t smm_enabled;
};
@@ -139,6 +140,8 @@ static void i440fx_update_memory_mappings(PCII440FXState *d)
pd->config[I440FX_PAM + ((i + 1) / 2)]);
}
smram_update(&d->smram_region, pd->config[I440FX_SMRAM], d->smm_enabled);
+ memory_region_set_enabled(&d->smram,
+ pd->config[I440FX_SMRAM] & SMRAM_G_SMRAME);
memory_region_transaction_commit();
}
@@ -346,11 +349,23 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
pc_pci_as_mapping_init(OBJECT(f), f->system_memory,
f->pci_address_space);
+ /* if *disabled* show SMRAM to all CPUs */
memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
f->pci_address_space, 0xa0000, 0x20000);
memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
&f->smram_region, 1);
memory_region_set_enabled(&f->smram_region, false);
+
+ /* smram, as seen by SMM CPUs */
+ memory_region_init(&f->smram, OBJECT(d), "smram", 1ull << 32);
+ memory_region_set_enabled(&f->smram, true);
+ memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low",
+ f->system_memory, 0xa0000, 0x20000);
+ memory_region_set_enabled(&f->low_smram, true);
+ memory_region_add_subregion(&f->smram, 0xa0000, &f->low_smram);
+ object_property_add_alias(qdev_get_machine(), "smram",
+ OBJECT(&f->smram), ".", NULL);
+
init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
&f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
for (i = 0; i < 12; ++i) {
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index c8827cc..de8326a 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -270,6 +270,8 @@ static void mch_update_smram(MCHPCIState *mch)
memory_region_transaction_begin();
smram_update(&mch->smram_region, pd->config[MCH_HOST_BRIDGE_SMRAM],
mch->smm_enabled);
+ memory_region_set_enabled(&mch->smram,
+ pd->config[MCH_HOST_BRIDGE_SMRAM] &
SMRAM_G_SMRAME);
memory_region_transaction_commit();
}
@@ -399,13 +401,24 @@ static void mch_realize(PCIDevice *d, Error **errp)
pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory,
mch->pci_address_space);
- /* smram */
+ /* if *disabled* show SMRAM to all CPUs */
cpu_smm_register(&mch_set_smm, mch);
memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region",
mch->pci_address_space, 0xa0000, 0x20000);
memory_region_add_subregion_overlap(mch->system_memory, 0xa0000,
&mch->smram_region, 1);
memory_region_set_enabled(&mch->smram_region, false);
+
+ /* smram, as seen by SMM CPUs */
+ memory_region_init(&mch->smram, OBJECT(mch), "smram", 1ull << 32);
+ memory_region_set_enabled(&mch->smram, true);
+ memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low",
+ mch->system_memory, 0xa0000, 0x20000);
+ memory_region_set_enabled(&mch->low_smram, true);
+ memory_region_add_subregion(&mch->smram, 0xa0000, &mch->low_smram);
+ object_property_add_const_link(qdev_get_machine(), "smram",
+ OBJECT(&mch->smram), &error_abort);
+
init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory,
mch->pci_address_space, &mch->pam_regions[0],
PAM_BIOS_BASE, PAM_BIOS_SIZE);
diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
index 96d4cdc..4c9eacc 100644
--- a/include/hw/pci-host/q35.h
+++ b/include/hw/pci-host/q35.h
@@ -53,6 +53,7 @@ typedef struct MCHPCIState {
MemoryRegion *address_space_io;
PAMMemoryRegion pam_regions[13];
MemoryRegion smram_region;
+ MemoryRegion smram, low_smram;
PcPciInfo pci_info;
uint8_t smm_enabled;
ram_addr_t below_4g_mem_size;
--
1.8.3.1
- Re: [Qemu-devel] [PATCH 10/31] vl: allow full-blown QemuOpts syntax for -global, (continued)
- [Qemu-devel] [PATCH 09/31] pflash_cfi01: add secure property, Paolo Bonzini, 2015/05/11
- [Qemu-devel] [PATCH 12/31] vl: run "late" notifiers immediately, Paolo Bonzini, 2015/05/11
- [Qemu-devel] [PATCH 13/31] target-i386: create a separate AddressSpace for each CPU, Paolo Bonzini, 2015/05/11
- [Qemu-devel] [PATCH 11/31] qom: add object_property_add_const_link, Paolo Bonzini, 2015/05/11
- [Qemu-devel] [PATCH 14/31] hw/i386: add a separate region that tracks the SMRAME bit,
Paolo Bonzini <=
- [Qemu-devel] [PATCH 15/31] target-i386: use memory API to implement SMRAM, Paolo Bonzini, 2015/05/11
- [Qemu-devel] [PATCH 16/31] hw/i386: remove smram_update, Paolo Bonzini, 2015/05/11
- [Qemu-devel] [PATCH 17/31] q35: implement high SMRAM, Paolo Bonzini, 2015/05/11
- [Qemu-devel] [PATCH 18/31] q35: fix ESMRAMC default, Paolo Bonzini, 2015/05/11
- [Qemu-devel] [PATCH 19/31] q35: add config space wmask for SMRAM and ESMRAMC, Paolo Bonzini, 2015/05/11
- [Qemu-devel] [PATCH 22/31] q35: implement TSEG, Paolo Bonzini, 2015/05/11
- [Qemu-devel] [PATCH 21/31] q35: add test for SMRAM.D_LCK, Paolo Bonzini, 2015/05/11