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[Qemu-devel] [PATCH target-arm v7 00/15] Next Generation Xilinx Zynq SoC
From: |
Peter Crosthwaite |
Subject: |
[Qemu-devel] [PATCH target-arm v7 00/15] Next Generation Xilinx Zynq SoC |
Date: |
Wed, 6 May 2015 15:50:22 -0700 |
Hi Peter and all,
Xilinx's next gen SoC has been announced. This series adds a SoC and
board.
Series start with addition of ARM cortex A53 support (P1 and P2). The
Soc skeleton is then added with GIC, EMACs and UARTs added. The
pre-existing models for GEM and UART are not SoC friendly (no visible
state struct), so those are refactored for SoC.
Create a model of the EP108 board. Currently this doesn't have any
EP108 specific features but is a usable board exposing the user visible
features of the raw SoC.
See individual patches for detailed change logs.
changed since v6 (Edgar review):
Added GIC region size macro
Added GIC alises
changed since v4:
Addressed PMM and Alistair Reviews
changed since v3:
Included CPU thread kick fix
Addressed Alistair review
changed since v2:
Fix CPU child prop adder
Add DTS compat string
changed since v1:
Addressed Alistair review (individual changes on resp. patches)
Changed board name to EP108
Changed naming scheme to "zynqmp" / "ZYNQMP" (Michal review)
Regards,
Peter
Peter Crosthwaite (15):
target-arm: cpu64: generalise name of A57 regs
target-arm: cpu64: Add support for cortex-a53
arm: Introduce Xilinx ZynqMP SoC
intc: arm_gic: Macroify the MemoryRegion size
arm: xlnx-zynqmp: Add GIC
arm: xlnx-zynqmp: Connect CPU Timers to GIC
net: cadence_gem: Clean up variable names
net: cadence_gem: Split state struct and type into header
arm: xlnx-zynqmp: Add GEM support
char: cadence_uart: Clean up variable names
char: cadence_uart: Split state struct and type into header
arm: xlnx-zynqmp: Add UART support
arm: Add xlnx-ep108 machine
arm: xlnx-ep108: Add external RAM
arm: xlnx-ep108: Add bootloading
default-configs/aarch64-softmmu.mak | 2 +-
hw/arm/Makefile.objs | 1 +
hw/arm/xlnx-ep108.c | 82 ++++++++++++++
hw/arm/xlnx-zynqmp.c | 211 ++++++++++++++++++++++++++++++++++++
hw/char/cadence_uart.c | 115 ++++++++------------
hw/intc/arm_gic.c | 2 +-
hw/net/cadence_gem.c | 95 +++++-----------
include/hw/arm/xlnx-zynqmp.h | 57 ++++++++++
include/hw/char/cadence_uart.h | 53 +++++++++
include/hw/intc/arm_gic.h | 2 +
include/hw/net/cadence_gem.h | 73 +++++++++++++
target-arm/cpu64.c | 61 ++++++++++-
12 files changed, 611 insertions(+), 143 deletions(-)
create mode 100644 hw/arm/xlnx-ep108.c
create mode 100644 hw/arm/xlnx-zynqmp.c
create mode 100644 include/hw/arm/xlnx-zynqmp.h
create mode 100644 include/hw/char/cadence_uart.h
create mode 100644 include/hw/net/cadence_gem.h
--
2.4.0.3.ge0ccc3b.dirty
- [Qemu-devel] [PATCH target-arm v7 00/15] Next Generation Xilinx Zynq SoC,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH target-arm v7 06/15] arm: xlnx-zynqmp: Connect CPU Timers to GIC, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 04/15] intc: arm_gic: Macroify the MemoryRegion size, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 03/15] arm: Introduce Xilinx ZynqMP SoC, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 02/15] target-arm: cpu64: Add support for cortex-a53, Peter Crosthwaite, 2015/05/06
- [Qemu-devel] [PATCH target-arm v7 05/15] arm: xlnx-zynqmp: Add GIC, Peter Crosthwaite, 2015/05/06