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[Qemu-devel] [PATCH target-arm v4 00/16] Next Generation Xilinx Zynq SoC
From: |
Peter Crosthwaite |
Subject: |
[Qemu-devel] [PATCH target-arm v4 00/16] Next Generation Xilinx Zynq SoC |
Date: |
Mon, 23 Mar 2015 04:05:08 -0700 |
Hi Peter and all,
Xilinx's next gen SoC has been announced. This series adds a SoC and
board.
Series start with addition of ARM cortex A53 support (P1 and P2). The
Soc skeleton is then added with GIC, EMACs and UARTs are added. The
pre-existing models for GEM and UART are not SoC friendly (no visible
state struct), so those are refactored for SoC.
Create a model of the EP108 board. Currently this doesn't have any
EP108 specific features but is a usable board exposing the user visible
features of the raw SoC.
changed since v3:
Included CPU thread kick fix
Addressed Alistair review
changed since v2:
Fix CPU child prop adder
Add DTS compat string
changed since v1:
Addressed Alistair review (individual changes on resp. patches)
Changed board name to EP108
Changed naming scheme to "zynqmp" / "ZYNQMP" (Michal review)
Regards,
Peter
Peter Crosthwaite (16):
cpus: Don't kick un-realized cpus.
target-arm: cpu64: Factor out ARM cortex init
target-arm: cpu64: Add support for cortex-a53
arm: Introduce Xilinx ZynqMP SoC
arm: xlnx-zynqmp: Add GIC
arm: xlnx-zynqmp: Connect CPU Timers to GIC
net: cadence_gem: Clean up variable names
net: cadence_gem: Split state struct and type into header
arm: xilinx-zynqmp: Add GEM support
char: cadence_uart: Clean up variable names
char: cadence_uart: Split state struct and type into header
arm: xilinx-zynqmp: Add UART support
arm: Add xlnx-ep108 machine
arm: xilinx-ep108: Add external RAM
arm: xilinx-ep108: Add bootloading
arm: xlnx-zynqmp: Add PSCI setup
cpus.c | 2 +-
default-configs/aarch64-softmmu.mak | 2 +-
hw/arm/Makefile.objs | 1 +
hw/arm/xlnx-ep108.c | 82 ++++++++++++++++++
hw/arm/xlnx-zynqmp.c | 168 ++++++++++++++++++++++++++++++++++++
hw/char/cadence_uart.c | 115 ++++++++++--------------
hw/net/cadence_gem.c | 95 ++++++--------------
include/hw/arm/xlnx-zynqmp.h | 29 +++++++
include/hw/char/cadence_uart.h | 35 ++++++++
include/hw/net/cadence_gem.h | 49 +++++++++++
target-arm/cpu64.c | 50 ++++++++---
11 files changed, 476 insertions(+), 152 deletions(-)
create mode 100644 hw/arm/xlnx-ep108.c
create mode 100644 hw/arm/xlnx-zynqmp.c
create mode 100644 include/hw/arm/xlnx-zynqmp.h
create mode 100644 include/hw/char/cadence_uart.h
create mode 100644 include/hw/net/cadence_gem.h
--
2.3.1.2.g90df61e.dirty
- [Qemu-devel] [PATCH target-arm v4 00/16] Next Generation Xilinx Zynq SoC,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH target-arm v4 01/16] cpus: Don't kick un-realized cpus., Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 02/16] target-arm: cpu64: Factor out ARM cortex init, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 04/16] arm: Introduce Xilinx ZynqMP SoC, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 03/16] target-arm: cpu64: Add support for cortex-a53, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 05/16] arm: xlnx-zynqmp: Add GIC, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 08/16] net: cadence_gem: Split state struct and type into header, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 07/16] net: cadence_gem: Clean up variable names, Peter Crosthwaite, 2015/03/23
- [Qemu-devel] [PATCH target-arm v4 13/16] arm: Add xlnx-ep108 machine, Peter Crosthwaite, 2015/03/23