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Re: [Qemu-devel] [PATCH 02/11] target-arm: Extend NZCF to 64 bits
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH 02/11] target-arm: Extend NZCF to 64 bits |
Date: |
Tue, 10 Mar 2015 16:08:55 +0000 |
On 19 February 2015 at 21:14, Richard Henderson <address@hidden> wrote:
> The resulting aarch64 translation is a bit cleaner.
> Sign-extending from 32-bits is simpler than having
> to use setcond to narrow from 64-bits.
>
> Signed-off-by: Richard Henderson <address@hidden>
> @@ -4545,6 +4548,9 @@ void aarch64_sync_64_to_32(CPUARMState *env)
> env->regs[i] = env->xregs[i];
> }
>
> + /* Need to compress Z into the low bits. */
> + env->ZF = (env->ZF != 0);
> +
I really don't like this. Having state with a different format
in 32-bit and 64-bit modes is asking for trouble -- the bits
we already have to convert are already awkward enough.
I'd much rather we stuck with a format where env->ZF is
the same regardless of register width, as we have now.
-- PMM
- Re: [Qemu-devel] [PATCH 02/11] target-arm: Extend NZCF to 64 bits,
Peter Maydell <=