[Qemu-devel] [PATCH 1/5] target-tile: Firstly add to qemu with minimized features

[Chen Gang S]

It almost likes a template for adding an architecture target.

Signed-off-by: Chen Gang <address@hidden>
---
 configure                             |   7 ++
 default-configs/tilegx-linux-user.mak |   1 +
 target-tile/Makefile.objs             |   1 +
 target-tile/cpu-qom.h                 |  72 +++++++++++++++
 target-tile/cpu.c                     | 159 ++++++++++++++++++++++++++++++++++
 target-tile/cpu.h                     |  84 ++++++++++++++++++
 target-tile/helper.h                  |   0
 target-tile/translate.c               |  54 ++++++++++++
 8 files changed, 378 insertions(+)
 create mode 100644 default-configs/tilegx-linux-user.mak
 create mode 100644 target-tile/Makefile.objs
 create mode 100644 target-tile/cpu-qom.h
 create mode 100644 target-tile/cpu.c
 create mode 100644 target-tile/cpu.h
 create mode 100644 target-tile/helper.h
 create mode 100644 target-tile/translate.c

diff --git a/configure b/configure
index 7ba4bcb..ffb4d56 100755
--- a/configure
+++ b/configure
@@ -5191,6 +5191,9 @@ case "$target_name" in
   s390x)
     gdb_xml_files="s390x-core64.xml s390-acr.xml s390-fpr.xml"
   ;;
+  tilegx)
+    TARGET_ARCH=tile
+  ;;
   unicore32)
   ;;
   xtensa|xtensaeb)
@@ -5363,6 +5366,10 @@ for i in $ARCH $TARGET_BASE_ARCH ; do
     echo "CONFIG_SPARC_DIS=y"  >> $config_target_mak
     echo "CONFIG_SPARC_DIS=y"  >> config-all-disas.mak
   ;;
+  tilegx*)
+    echo "CONFIG_TILE_DIS=y"  >> $config_target_mak
+    echo "CONFIG_TILE_DIS=y"  >> config-all-disas.mak
+  ;;
   xtensa*)
     echo "CONFIG_XTENSA_DIS=y"  >> $config_target_mak
     echo "CONFIG_XTENSA_DIS=y"  >> config-all-disas.mak
diff --git a/default-configs/tilegx-linux-user.mak 
b/default-configs/tilegx-linux-user.mak
new file mode 100644
index 0000000..3e47493
--- /dev/null
+++ b/default-configs/tilegx-linux-user.mak
@@ -0,0 +1 @@
+# Default configuration for tilegx-linux-user
diff --git a/target-tile/Makefile.objs b/target-tile/Makefile.objs
new file mode 100644
index 0000000..dcf2fe4
--- /dev/null
+++ b/target-tile/Makefile.objs
@@ -0,0 +1 @@
+obj-y += cpu.o translate.o
diff --git a/target-tile/cpu-qom.h b/target-tile/cpu-qom.h
new file mode 100644
index 0000000..6026b81
--- /dev/null
+++ b/target-tile/cpu-qom.h
@@ -0,0 +1,72 @@
+/*
+ * QEMU Tile CPU
+ *
+ * Copyright (c) 2015 Chen Gang
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+#ifndef QEMU_TILE_CPU_QOM_H
+#define QEMU_TILE_CPU_QOM_H
+
+#include "qom/cpu.h"
+
+#define TYPE_TILE_CPU "tile-cpu"
+
+#define TILE_CPU_CLASS(klass) \
+    OBJECT_CLASS_CHECK(TileCPUClass, (klass), TYPE_TILE_CPU)
+#define TILE_CPU(obj) \
+    OBJECT_CHECK(TileCPU, (obj), TYPE_TILE_CPU)
+#define TILE_CPU_GET_CLASS(obj) \
+    OBJECT_GET_CLASS(TileCPUClass, (obj), TYPE_TILE_CPU)
+
+/**
+ * TileCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_reset: The parent class' reset handler.
+ *
+ * A Tile CPU model.
+ */
+typedef struct TileCPUClass {
+    /*< private >*/
+    CPUClass parent_class;
+    /*< public >*/
+
+    DeviceRealize parent_realize;
+    void (*parent_reset)(CPUState *cpu);
+} TileCPUClass;
+
+/**
+ * TileCPU:
+ * @env: #CPUTLState
+ *
+ * A Tile CPU.
+ */
+typedef struct TileCPU {
+    /*< private >*/
+    CPUState parent_obj;
+    uint64_t base_vectors;
+    /*< public >*/
+
+    CPUTLState env;
+} TileCPU;
+
+static inline TileCPU *tile_env_get_cpu(CPUTLState *env)
+{
+    return container_of(env, TileCPU, env);
+}
+
+#define ENV_GET_CPU(e) CPU(tile_env_get_cpu(e))
+
+#endif
diff --git a/target-tile/cpu.c b/target-tile/cpu.c
new file mode 100644
index 0000000..365ec7a
--- /dev/null
+++ b/target-tile/cpu.c
@@ -0,0 +1,159 @@
+/*
+ * QEMU Tile CPU
+ *
+ *  Copyright (c) 2015 Chen Gang
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "cpu.h"
+#include "qemu-common.h"
+#include "hw/qdev-properties.h"
+#include "migration/vmstate.h"
+
+TileCPU *cpu_tile_init(const char *cpu_model)
+{
+    TileCPU *cpu;
+
+    cpu = TILE_CPU(object_new(TYPE_TILE_CPU));
+
+    object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
+
+    return cpu;
+}
+
+static void tile_cpu_set_pc(CPUState *cs, vaddr value)
+{
+}
+
+static bool tile_cpu_has_work(CPUState *cs)
+{
+    return true;
+}
+
+static void tile_cpu_reset(CPUState *s)
+{
+    TileCPU *cpu = TILE_CPU(s);
+    TileCPUClass *mcc = TILE_CPU_GET_CLASS(cpu);
+    CPUTLState *env = &cpu->env;
+
+    mcc->parent_reset(s);
+
+    memset(env, 0, sizeof(CPUTLState));
+    tlb_flush(s, 1);
+}
+
+static void tile_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+    CPUState *cs = CPU(dev);
+    TileCPUClass *mcc = TILE_CPU_GET_CLASS(dev);
+
+    cpu_reset(cs);
+    qemu_init_vcpu(cs);
+
+    mcc->parent_realize(dev, errp);
+}
+
+static void tile_tcg_init(void)
+{
+}
+
+static void tile_cpu_initfn(Object *obj)
+{
+    CPUState *cs = CPU(obj);
+    TileCPU *cpu = TILE_CPU(obj);
+    CPUTLState *env = &cpu->env;
+    static bool tcg_initialized;
+
+    cs->env_ptr = env;
+    cpu_exec_init(env);
+
+    if (tcg_enabled() && !tcg_initialized) {
+        tcg_initialized = true;
+        tile_tcg_init();
+    }
+}
+
+static const VMStateDescription vmstate_tile_cpu = {
+    .name = "cpu",
+    .unmigratable = 1,
+};
+
+static Property tile_properties[] = {
+    DEFINE_PROP_UINT64("tile.base-vectors", TileCPU, base_vectors, 0),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void tile_cpu_do_interrupt(CPUState *cs)
+{
+    cs->exception_index = -1;
+}
+
+static int tile_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
+                            int mmu_idx)
+{
+    cpu_dump_state(cs, stderr, fprintf, 0);
+    return 1;
+}
+
+static bool tile_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+{
+    if (interrupt_request & CPU_INTERRUPT_HARD) {
+        tile_cpu_do_interrupt(cs);
+        return true;
+    }
+    return false;
+}
+
+static void tile_cpu_class_init(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+    CPUClass *cc = CPU_CLASS(oc);
+    TileCPUClass *mcc = TILE_CPU_CLASS(oc);
+
+    mcc->parent_realize = dc->realize;
+    dc->realize = tile_cpu_realizefn;
+
+    mcc->parent_reset = cc->reset;
+    cc->reset = tile_cpu_reset;
+
+    cc->has_work = tile_cpu_has_work;
+    cc->do_interrupt = tile_cpu_do_interrupt;
+    cc->cpu_exec_interrupt = tile_cpu_exec_interrupt;
+    cc->dump_state = NULL;
+    cc->set_pc = tile_cpu_set_pc;
+    cc->gdb_read_register = NULL;
+    cc->gdb_write_register = NULL;
+    cc->handle_mmu_fault = tile_cpu_handle_mmu_fault;
+    dc->vmsd = &vmstate_tile_cpu;
+    dc->props = tile_properties;
+    cc->gdb_num_core_regs = 0;
+}
+
+static const TypeInfo tile_cpu_type_info = {
+    .name = TYPE_TILE_CPU,
+    .parent = TYPE_CPU,
+    .instance_size = sizeof(TileCPU),
+    .instance_init = tile_cpu_initfn,
+    .class_size = sizeof(TileCPUClass),
+    .class_init = tile_cpu_class_init,
+};
+
+static void tile_cpu_register_types(void)
+{
+    type_register_static(&tile_cpu_type_info);
+}
+
+type_init(tile_cpu_register_types)
diff --git a/target-tile/cpu.h b/target-tile/cpu.h
new file mode 100644
index 0000000..b52ad75
--- /dev/null
+++ b/target-tile/cpu.h
@@ -0,0 +1,84 @@
+/*
+ *  Tile virtual CPU header
+ *
+ *  Copyright (c) 2015 Chen Gang
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef CPU_TILE_H
+#define CPU_TILE_H
+
+#include "config.h"
+#include "qemu-common.h"
+
+#define TARGET_LONG_BITS 64
+
+#define CPUArchState struct CPUTLState
+
+#include "exec/cpu-defs.h"
+#include "fpu/softfloat.h"
+
+/* Tilegx register alias */
+#define TILE_R_RE  0   /*  0 register, for function/syscall return value */
+#define TILE_R_NR  10  /* 10 register, for syscall number */
+#define TILE_R_BP  52  /* 52 register, optional frame pointer */
+#define TILE_R_TP  53  /* TP register, thread local storage data */
+#define TILE_R_SP  54  /* SP register, stack pointer */
+#define TILE_R_PC  55  /* LR register, pc pointer */
+
+typedef struct CPUTLState {
+    uint64_t regs[56];
+    CPU_COMMON
+} CPUTLState;
+
+#include "cpu-qom.h"
+
+/* Tilegx memory attributes */
+#define TARGET_PAGE_BITS 16  /* Tilegx uses 64KB page size */
+#define MMAP_SHIFT TARGET_PAGE_BITS
+#define TARGET_PHYS_ADDR_SPACE_BITS 42 /* Tilegx is 42 bit physical address */
+#define TARGET_VIRT_ADDR_SPACE_BITS 64 /* Tilegx has 64 bit virtual address */
+#define MMU_USER_IDX    0  /* independent from both qemu and architecture */
+
+#include "exec/cpu-all.h"
+
+int cpu_tile_exec(CPUTLState *s);
+int cpu_tile_signal_handler(int host_signum, void *pinfo, void *puc);
+
+#define cpu_exec cpu_tile_exec
+#define cpu_gen_code cpu_tile_gen_code
+#define cpu_signal_handler cpu_tile_signal_handler
+
+TileCPU *cpu_tile_init(const char *cpu_model);
+
+static inline CPUTLState *cpu_init(const char *cpu_model)
+{
+    TileCPU *cpu = cpu_tile_init(cpu_model);
+    if (cpu == NULL) {
+        return NULL;
+    }
+    return &cpu->env;
+}
+
+static inline void cpu_get_tb_cpu_state(CPUTLState *env, target_ulong *pc,
+                                        target_ulong *cs_base, int *flags)
+{
+    *pc = env->regs[TILE_R_PC];
+    *cs_base = 0;
+    *flags = 0;
+}
+
+#include "exec/exec-all.h"
+
+#endif
diff --git a/target-tile/helper.h b/target-tile/helper.h
new file mode 100644
index 0000000..e69de29
diff --git a/target-tile/translate.c b/target-tile/translate.c
new file mode 100644
index 0000000..d9fbf71
--- /dev/null
+++ b/target-tile/translate.c
@@ -0,0 +1,54 @@
+/*
+ * QEMU Tile CPU
+ *
+ *  Copyright (c) 2015 Chen Gang
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "cpu.h"
+#include "disas/disas.h"
+#include "tcg-op.h"
+#include "exec/helper-proto.h"
+#include "exec/cpu_ldst.h"
+#include "exec/helper-gen.h"
+
+static inline void gen_intermediate_code_internal(TileCPU *cpu,
+                                                  TranslationBlock *tb,
+                                                  bool search_pc)
+{
+    /*
+     * FIXME: after load elf64 tilegx binary successfully, it will quit, at
+     * present, and will implement the related features next.
+     */
+    fprintf(stderr, "\nLoad elf64 tilegx successfully\n");
+    fprintf(stderr, "reach code start position: [" TARGET_FMT_lx "] %s\n\n",
+            tb->pc, lookup_symbol(tb->pc));
+    exit(0);
+}
+
+void gen_intermediate_code(CPUTLState *env, struct TranslationBlock *tb)
+{
+    gen_intermediate_code_internal(tile_env_get_cpu(env), tb, false);
+}
+
+void gen_intermediate_code_pc(CPUTLState *env, struct TranslationBlock *tb)
+{
+    gen_intermediate_code_internal(tile_env_get_cpu(env), tb, true);
+}
+
+void restore_state_to_opc(CPUTLState *env, TranslationBlock *tb, int pc_pos)
+{
+}
-- 
1.9.3 (Apple Git-50)