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[Qemu-devel] [PULL v2 2/9] target-tricore: Several translator and cpu mo
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PULL v2 2/9] target-tricore: Several translator and cpu model fixes |
Date: |
Tue, 27 Jan 2015 12:09:18 +0000 |
Fix tc1796 cpu model using wrong ISA version.
Fix cond_add sometimes writing back wrong result.
Fix RCR_SEL and RCR_SELN using wrong registers for result and cond.
Signed-off-by: Bastian Koppelmann <address@hidden>
---
target-tricore/cpu.c | 2 +-
target-tricore/op_helper.c | 1 +
target-tricore/translate.c | 6 +++---
3 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-tricore/cpu.c b/target-tricore/cpu.c
index abe16fa..2ba0cf4 100644
--- a/target-tricore/cpu.c
+++ b/target-tricore/cpu.c
@@ -118,7 +118,7 @@ static void tc1796_initfn(Object *obj)
{
TriCoreCPU *cpu = TRICORE_CPU(obj);
- set_feature(&cpu->env, TRICORE_FEATURE_13);
+ set_feature(&cpu->env, TRICORE_FEATURE_131);
}
static void aurix_initfn(Object *obj)
diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c
index 5704549..ec2a0cc 100644
--- a/target-tricore/op_helper.c
+++ b/target-tricore/op_helper.c
@@ -255,6 +255,7 @@ target_ulong helper_mul_suov(CPUTriCoreState *env,
target_ulong r1,
int64_t t1 = extract64(r1, 0, 32);
int64_t t2 = extract64(r2, 0, 32);
int64_t result = t1 * t2;
+
return suov32(env, result);
}
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index def7f4a..61518f3 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -745,7 +745,7 @@ static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv
r2, TCGv r3,
tcg_gen_and_tl(temp, temp, mask);
tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
/* write back result */
- tcg_gen_movcond_tl(cond, r3, r4, t0, result, r3);
+ tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
tcg_temp_free(t0);
tcg_temp_free(temp);
@@ -3898,7 +3898,7 @@ static void decode_rcr_cond_select(CPUTriCoreState *env,
DisasContext *ctx)
case OPC2_32_RCR_SEL:
temp = tcg_const_i32(0);
temp2 = tcg_const_i32(const9);
- tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r4], temp,
+ tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
cpu_gpr_d[r1], temp2);
tcg_temp_free(temp);
tcg_temp_free(temp2);
@@ -3906,7 +3906,7 @@ static void decode_rcr_cond_select(CPUTriCoreState *env,
DisasContext *ctx)
case OPC2_32_RCR_SELN:
temp = tcg_const_i32(0);
temp2 = tcg_const_i32(const9);
- tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r4], temp,
+ tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
cpu_gpr_d[r1], temp2);
tcg_temp_free(temp);
tcg_temp_free(temp2);
--
2.2.2
- [Qemu-devel] [PULL v2 0/9] tricore patches, Bastian Koppelmann, 2015/01/27
- [Qemu-devel] [PULL v2 2/9] target-tricore: Several translator and cpu model fixes,
Bastian Koppelmann <=
- [Qemu-devel] [PULL v2 3/9] target-tricore: calculate av bits before saturation, Bastian Koppelmann, 2015/01/27
- [Qemu-devel] [PULL v2 4/9] target-tricore: Fix bugs found by coverity, Bastian Koppelmann, 2015/01/27
- [Qemu-devel] [PULL v2 1/9] target-tricore: Add missing ULL suffix on 64 bit constant, Bastian Koppelmann, 2015/01/27
- [Qemu-devel] [PULL v2 5/9] target-tricore: split up suov32 into suov32_pos and suov32_neg, Bastian Koppelmann, 2015/01/27
- [Qemu-devel] [PULL v2 8/9] target-tricore: Add instructions of RRPW opcode format, Bastian Koppelmann, 2015/01/27
- [Qemu-devel] [PULL v2 7/9] target-tricore: Add instructions of RR2 opcode format, Bastian Koppelmann, 2015/01/27
- [Qemu-devel] [PULL v2 9/9] target-tricore: Add instructions of RRR opcode format, Bastian Koppelmann, 2015/01/27
- [Qemu-devel] [PULL v2 6/9] target-tricore: Add instructions of RR1 opcode format, that have 0x93 as first opcode, Bastian Koppelmann, 2015/01/27
- Re: [Qemu-devel] [PULL v2 0/9] tricore patches, Peter Maydell, 2015/01/27