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[Qemu-devel] [PULL 02/31] target-arm: Merge EL3 CP15 register lists
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 02/31] target-arm: Merge EL3 CP15 register lists |
Date: |
Tue, 23 Dec 2014 13:53:58 +0000 |
From: Greg Bellows <address@hidden>
Merge of the v8_el2_cp_reginfo and el3_cp_reginfo ARMCPRegInfo lists.
Previously, some EL3 registers were restricted to the ARMv8 list under the
impression that they were not needed on ARMv7. However, this is not the case
as the ARMv7/32-bit variants rely on the ARMv8/64-bit variants to handle
migration and reset. For this reason they must always exist.
Signed-off-by: Greg Bellows <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 55 +++++++++++++++++++++++------------------------------
1 file changed, 24 insertions(+), 31 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 96abbed..3ef0f1f 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2413,7 +2413,30 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
REGINFO_SENTINEL
};
-static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
+static const ARMCPRegInfo el3_cp_reginfo[] = {
+ { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
+ .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
+ .resetvalue = 0, .writefn = scr_write },
+ { .name = "SCR", .type = ARM_CP_NO_MIGRATE,
+ .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
+ .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState,
cp15.scr_el3),
+ .resetfn = arm_cp_reset_ignore, .writefn = scr_write },
+ { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
+ .access = PL3_RW, .resetvalue = 0,
+ .fieldoffset = offsetof(CPUARMState, cp15.sder) },
+ { .name = "SDER",
+ .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1,
+ .access = PL3_RW, .resetvalue = 0,
+ .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) },
+ /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */
+ { .name = "NSACR", .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
+ .access = PL3_W | PL1_R, .resetvalue = 0,
+ .fieldoffset = offsetof(CPUARMState, cp15.nsacr) },
+ { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
+ .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0,
+ .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
{ .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
.access = PL3_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
@@ -2451,33 +2474,6 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
REGINFO_SENTINEL
};
-static const ARMCPRegInfo el3_cp_reginfo[] = {
- { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
- .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
- .resetvalue = 0, .writefn = scr_write },
- { .name = "SCR", .type = ARM_CP_NO_MIGRATE,
- .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
- .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState,
cp15.scr_el3),
- .resetfn = arm_cp_reset_ignore, .writefn = scr_write },
- { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
- .access = PL3_RW, .resetvalue = 0,
- .fieldoffset = offsetof(CPUARMState, cp15.sder) },
- { .name = "SDER",
- .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1,
- .access = PL3_RW, .resetvalue = 0,
- .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) },
- /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */
- { .name = "NSACR", .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
- .access = PL3_W | PL1_R, .resetvalue = 0,
- .fieldoffset = offsetof(CPUARMState, cp15.nsacr) },
- { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
- .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0,
- .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
- REGINFO_SENTINEL
-};
-
static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
/* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
@@ -3077,9 +3073,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
}
if (arm_feature(env, ARM_FEATURE_EL3)) {
- if (arm_feature(env, ARM_FEATURE_V8)) {
- define_arm_cp_regs(cpu, v8_el3_cp_reginfo);
- }
define_arm_cp_regs(cpu, el3_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_MPU)) {
--
1.9.1
- [Qemu-devel] [PULL 25/31] exec: allows 8-byte accesses in subpage_ops, (continued)
- [Qemu-devel] [PULL 25/31] exec: allows 8-byte accesses in subpage_ops, Peter Maydell, 2014/12/23
- [Qemu-devel] [PULL 23/31] fw_cfg_mem: max access size and region size are the same for data register, Peter Maydell, 2014/12/23
- [Qemu-devel] [PULL 26/31] fw_cfg_mem: introduce the "data_width" property, Peter Maydell, 2014/12/23
- [Qemu-devel] [PULL 17/31] target-arm: Set CPU has_el3 prop during virt init, Peter Maydell, 2014/12/23
- [Qemu-devel] [PULL 20/31] target-arm: add cpu feature EL3 to CPUs with Security Extensions, Peter Maydell, 2014/12/23
- [Qemu-devel] [PULL 15/31] target-arm: Add arm_boot_info secure_boot control, Peter Maydell, 2014/12/23
- [Qemu-devel] [PULL 14/31] target-arm: Add ARMCPU secure property, Peter Maydell, 2014/12/23
- [Qemu-devel] [PULL 12/31] target-arm: Add virt machine secure property, Peter Maydell, 2014/12/23
- [Qemu-devel] [PULL 01/31] audio: Don't free hw resources until after hw backend is stopped, Peter Maydell, 2014/12/23
- [Qemu-devel] [PULL 09/31] target-arm: Add vexpress machine secure property, Peter Maydell, 2014/12/23
- [Qemu-devel] [PULL 02/31] target-arm: Merge EL3 CP15 register lists,
Peter Maydell <=
- [Qemu-devel] [PULL 27/31] fw_cfg_mem: expose the "data_width" property with fw_cfg_init_mem_wide(), Peter Maydell, 2014/12/23
- [Qemu-devel] [PULL 29/31] hw/loader: split out load_image_gzipped_buffer(), Peter Maydell, 2014/12/23
- [Qemu-devel] [PULL 24/31] fw_cfg_mem: flip ctl_mem_ops and data_mem_ops to DEVICE_BIG_ENDIAN, Peter Maydell, 2014/12/23
- [Qemu-devel] [PULL 22/31] fw_cfg: move boards to fw_cfg_init_io() / fw_cfg_init_mem(), Peter Maydell, 2014/12/23
- [Qemu-devel] [PULL 18/31] target-arm: Breakout integratorcp and versatilepb cpu init, Peter Maydell, 2014/12/23
- [Qemu-devel] [PULL 16/31] target-arm: Enable CPU has_el3 prop during VE init, Peter Maydell, 2014/12/23
- [Qemu-devel] [PULL 07/31] target-arm: Add vexpress a9 & a15 machine objects, Peter Maydell, 2014/12/23
- [Qemu-devel] [PULL 19/31] target-arm: Disable EL3 on unsupported machines, Peter Maydell, 2014/12/23
- [Qemu-devel] [PULL 06/31] target-arm: Add vexpress class and machine types, Peter Maydell, 2014/12/23
- [Qemu-devel] [PULL 11/31] target-arm: Add virt class and machine types, Peter Maydell, 2014/12/23