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[Qemu-devel] [PULL 01/30] target-mips: Correct the handling of register
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 01/30] target-mips: Correct the handling of register #72 on writes |
Date: |
Tue, 16 Dec 2014 19:48:47 +0000 |
From: "Maciej W. Rozycki" <address@hidden>
Fix an off-by-one error in `mips_cpu_gdb_write_register' for register
matching how `mips_cpu_gdb_read_register' handles it. This register
slot is a fake anyway, there's nothing in hardware that corresponds to
it.
Signed-off-by: Maciej W. Rozycki <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/gdbstub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-mips/gdbstub.c b/target-mips/gdbstub.c
index f65fec2..7e3a604 100644
--- a/target-mips/gdbstub.c
+++ b/target-mips/gdbstub.c
@@ -90,7 +90,7 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t
*mem_buf, int n)
return sizeof(target_ulong);
}
if (env->CP0_Config1 & (1 << CP0C1_FP)
- && n >= 38 && n < 73) {
+ && n >= 38 && n < 72) {
if (n < 70) {
if (env->CP0_Status & (1 << CP0St_FR)) {
env->active_fpu.fpr[n - 38].d = tmp;
--
2.1.0
- [Qemu-devel] [PULL 00/30] target-mips queue, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 01/30] target-mips: Correct the handling of register #72 on writes,
Leon Alrae <=
- [Qemu-devel] [PULL 02/30] target-mips: Make CP1.FIR read-only here too, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 03/30] target-mips: Add 5KEc and 5KEf MIPS64r2 processors, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 09/30] target-mips: Fix formatting in `decode_opc', Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 10/30] target-mips: Make `helper_float_cvtw_s' consistent with the remaining helpers, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 11/30] target-mips: Remove unused `FLOAT_OP' macro, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 13/30] target-mips: Correct MIPS16/microMIPS branch size calculation, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 17/30] target-mips: Output CP0.Config2-5 in the register dump, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 14/30] target-mips: Correct the handling of writes to CP0.Status for MIPSr6, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 15/30] target-mips: Correct the writes to Status and Cause registers via gdbstub, Leon Alrae, 2014/12/16
- [Qemu-devel] [PULL 12/30] target-mips: Restore the order of helpers, Leon Alrae, 2014/12/16