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[Qemu-devel] [RFC PATCH] target-arm: protect cpu_exclusive_*.
From: |
fred . konrad |
Subject: |
[Qemu-devel] [RFC PATCH] target-arm: protect cpu_exclusive_*. |
Date: |
Tue, 16 Dec 2014 10:13:54 +0100 |
From: KONRAD Frederic <address@hidden>
This adds a lock to avoid multiple exclusive access at the same time in case of
TCG multithread.
Signed-off-by: KONRAD Frederic <address@hidden>
---
target-arm/cpu.c | 15 +++++++++++++++
target-arm/cpu.h | 3 +++
target-arm/helper.h | 3 +++
target-arm/op_helper.c | 10 ++++++++++
target-arm/translate.c | 6 ++++++
5 files changed, 37 insertions(+)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 5ce7350..a55017d 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -31,6 +31,19 @@
#include "sysemu/kvm.h"
#include "kvm_arm.h"
+/* Protect cpu_exclusive_* variable .*/
+QemuMutex cpu_exclusive_lock;
+
+inline void arm_exclusive_lock(void)
+{
+ qemu_mutex_lock(&cpu_exclusive_lock);
+}
+
+inline void arm_exclusive_unlock(void)
+{
+ qemu_mutex_unlock(&cpu_exclusive_lock);
+}
+
static void arm_cpu_set_pc(CPUState *cs, vaddr value)
{
ARMCPU *cpu = ARM_CPU(cs);
@@ -365,6 +378,7 @@ static void arm_cpu_initfn(Object *obj)
cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
if (!inited) {
inited = true;
+ qemu_mutex_init(&cpu_exclusive_lock);
arm_translate_init();
}
}
@@ -404,6 +418,7 @@ static void arm_cpu_finalizefn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
g_hash_table_destroy(cpu->cp_regs);
+ qemu_mutex_destroy(&cpu_exclusive_lock);
}
static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 7f80090..f01c9ef 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1539,4 +1539,7 @@ enum {
QEMU_PSCI_CONDUIT_HVC = 2,
};
+void arm_exclusive_lock(void);
+void arm_exclusive_unlock(void);
+
#endif
diff --git a/target-arm/helper.h b/target-arm/helper.h
index dec3728..ce07711 100644
--- a/target-arm/helper.h
+++ b/target-arm/helper.h
@@ -529,6 +529,9 @@ DEF_HELPER_2(dc_zva, void, env, i64)
DEF_HELPER_FLAGS_2(neon_pmull_64_lo, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(neon_pmull_64_hi, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_0(exclusive_lock, void)
+DEF_HELPER_0(exclusive_unlock, void)
+
#ifdef TARGET_AARCH64
#include "helper-a64.h"
#endif
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 62012c3..916772f 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -33,6 +33,16 @@ static void raise_exception(CPUARMState *env, int tt)
cpu_loop_exit(cs);
}
+void HELPER(exclusive_lock)(void)
+{
+ arm_exclusive_lock();
+}
+
+void HELPER(exclusive_unlock)(void)
+{
+ arm_exclusive_unlock();
+}
+
uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
uint32_t rn, uint32_t maxindex)
{
diff --git a/target-arm/translate.c b/target-arm/translate.c
index af51568..4a82ad5 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -7377,6 +7377,7 @@ static void gen_load_exclusive(DisasContext *s, int rt,
int rt2,
abort();
}
+ gen_helper_exclusive_lock();
if (size == 3) {
TCGv_i32 tmp2 = tcg_temp_new_i32();
TCGv_i32 tmp3 = tcg_temp_new_i32();
@@ -7392,11 +7393,14 @@ static void gen_load_exclusive(DisasContext *s, int rt,
int rt2,
store_reg(s, rt, tmp);
tcg_gen_extu_i32_i64(cpu_exclusive_addr, addr);
+ gen_helper_exclusive_unlock();
}
static void gen_clrex(DisasContext *s)
{
+ gen_helper_exclusive_lock();
tcg_gen_movi_i64(cpu_exclusive_addr, -1);
+ gen_helper_exclusive_unlock();
}
#ifdef CONFIG_USER_ONLY
@@ -7427,6 +7431,7 @@ static void gen_store_exclusive(DisasContext *s, int rd,
int rt, int rt2,
done_label = gen_new_label();
extaddr = tcg_temp_new_i64();
tcg_gen_extu_i32_i64(extaddr, addr);
+ gen_helper_exclusive_lock();
tcg_gen_brcond_i64(TCG_COND_NE, extaddr, cpu_exclusive_addr, fail_label);
tcg_temp_free_i64(extaddr);
@@ -7491,6 +7496,7 @@ static void gen_store_exclusive(DisasContext *s, int rd,
int rt, int rt2,
tcg_gen_movi_i32(cpu_R[rd], 1);
gen_set_label(done_label);
tcg_gen_movi_i64(cpu_exclusive_addr, -1);
+ gen_helper_exclusive_unlock();
}
#endif
--
1.9.0