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From: | Daniel Sanders |
Subject: | Re: [Qemu-devel] [PATCH] target-mips: add CPU definition for MIPS-II |
Date: | Mon, 15 Dec 2014 14:03:00 +0000 |
Hi, FWIW, the R6000 was a MIPS-II processor but I understand there was never a proper manual for it.
http://www.linux-mips.org/wiki/R6000 has a small amount of information but not enough to accurately fill in qemu's structure. > If this is really problematic for qemu, why don't we add an One other possibility is to use a real CPU name such as R6000 but use reasonable guesses where information is unavailable. Is that a good compromise? Daniel Sanders Leading Software Design Engineer, MIPS Processor IP Imagination Technologies Limited From: Vasileios Kalintiris
Hello Petar, From: Petar Jovanovic
address@hidden Adding (another) generic model for an old ISA revision is rather discouraged in QEMU trunk. Can you add a particular real CPU model? Regards, Petar ________________________________________ From: Vasileios Kalintiris Sent: 25 November 2014 11:04 To: address@hidden Cc: Leon Alrae; address@hidden Subject: [PATCH] target-mips: add CPU definition for MIPS-II Add mips2-generic among CPU definitions for MIPS. Signed-off-by: Vasileios Kalintiris <address@hidden> --- target-mips/translate_init.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 148b394..d4b1cd8 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -108,6 +108,29 @@ struct mips_def_t { static const mips_def_t mips_defs[] = { { + /* A generic CPU providing MIPS-II features. + FIXME: Eventually this should be replaced by a real CPU model. */ + .name = "mips2-generic", + .CP0_PRid = 0x00018000, + .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | + (0 << CP0C1_CA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x30000011, + .CP1_fcr0 = (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S), + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS2, + .mmu_type = MMU_TYPE_R4000, + }, + { .name = "4Kc", .CP0_PRid = 0x00018000, .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), -- ping |
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