Re: [Qemu-devel] [PATCH] ARM64: support access to more performance registers in AA64 mode

[Peter Maydell]

On 3 December 2014 at 20:25, Christopher Covington <address@hidden> wrote:
> Hi Chengyu,
>
> On 12/03/2014 02:12 AM, Chengyu Song wrote:

>>      { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 
>> = 1,
>>        .access = PL1_RW,
>>        .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
>>        .resetvalue = 0,
>>        .writefn = pmintenset_write, .raw_writefn = raw_write },
>> +    { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64,
>> +      .opc0 = 3, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
>> +      .access = PL1_RW,
>> +      .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
>> +      .resetvalue = 0,
>> +      .writefn = pmintenset_write, .raw_writefn = raw_write },
>
> Again, should .type = ARM_CP_NO_MIGRATE be used as this shares a variable with
> PMINTSET?

I think in this case and PMINTENCLR you can actually share a
single STATE_BOTH regdef, since the crn/crm/opc encodings
line up. Generally we prefer to do that where it works out.

thanks
-- PMM