[Qemu-devel] [PATCH] mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEP

[Maciej W. Rozycki]

Fix microMIPS MOVE16 and MOVEP instructions on 64-bit processors by 
using register addition operations.

This copies the approach taken with MIPS16 MOVE instructions (I8_MOV32R 
and I8_MOVR32 opcodes) and follows the observation that OPC_ADDU expands 
to tcg_gen_mov_tl whenever `rt' is 0 and `rs' is not, therefore copying 
`rs' to `rd' verbatim.  This is not the case with OPC_ADDIU where a 
sign-extension from bit #31 is made, unless in the uninteresting case of 
`rs' being 0, losing the upper 32 bits of the value copied for any 
proper 64-bit values.

This also serves as an optimization as one op is produced in generated 
code rather than two (again, unless `rs' is 0, where it doesn't change 
anything).

Signed-off-by: Maciej W. Rozycki <address@hidden>
---
 This is rather obvious, but I also pushed it through full bare-iron GCC 
regression testing with an o32 big-endian microMIPS multilib.  That 
includes several instances of both instructions.  No changes in results 
were observed with the patch applied compared to the original version.

 I wonder if all these move operations shouldn't actually be switched to 
using OPC_OR that is agnostic to the machine word size regardless of the 
operand selection.  But that is something to consider separately.

 So meanwhile, please apply.

  Maciej

qemu-umips-move.diff
Index: qemu-git-trunk/target-mips/translate.c
===================================================================
--- qemu-git-trunk.orig/target-mips/translate.c 2014-11-02 17:57:16.998924336 
+0000
+++ qemu-git-trunk/target-mips/translate.c      2014-11-02 17:57:19.498930155 
+0000
@@ -13492,8 +13492,8 @@ static int decode_micromips_opc (CPUMIPS
             rs = rs_rt_enc[enc_rs];
             rt = rs_rt_enc[enc_rt];
 
-            gen_arith_imm(ctx, OPC_ADDIU, rd, rs, 0);
-            gen_arith_imm(ctx, OPC_ADDIU, re, rt, 0);
+            gen_arith(ctx, OPC_ADDU, rd, rs, 0);
+            gen_arith(ctx, OPC_ADDU, re, rt, 0);
         }
         break;
     case LBU16:
@@ -13574,7 +13574,7 @@ static int decode_micromips_opc (CPUMIPS
             int rd = uMIPS_RD5(ctx->opcode);
             int rs = uMIPS_RS5(ctx->opcode);
 
-            gen_arith_imm(ctx, OPC_ADDIU, rd, rs, 0);
+            gen_arith(ctx, OPC_ADDU, rd, rs, 0);
         }
         break;
     case ANDI16: