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[Qemu-devel] [PATCH v10 09/26] target-arm: implement IRQ/FIQ routing to
From: |
Greg Bellows |
Subject: |
[Qemu-devel] [PATCH v10 09/26] target-arm: implement IRQ/FIQ routing to Monitor mode |
Date: |
Thu, 6 Nov 2014 09:50:56 -0600 |
From: Fabian Aggeler <address@hidden>
SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU
mode. When taking IRQ exception to monitor mode FIQ exception is
additionally masked.
Signed-off-by: Sergey Fedorov <address@hidden>
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 1be185d..3086c2c 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -4233,12 +4233,21 @@ void arm_cpu_do_interrupt(CPUState *cs)
/* Disable IRQ and imprecise data aborts. */
mask = CPSR_A | CPSR_I;
offset = 4;
+ if (env->cp15.scr_el3 & SCR_IRQ) {
+ /* IRQ routed to monitor mode */
+ new_mode = ARM_CPU_MODE_MON;
+ mask |= CPSR_F;
+ }
break;
case EXCP_FIQ:
new_mode = ARM_CPU_MODE_FIQ;
addr = 0x1c;
/* Disable FIQ, IRQ and imprecise data aborts. */
mask = CPSR_A | CPSR_I | CPSR_F;
+ if (env->cp15.scr_el3 & SCR_FIQ) {
+ /* FIQ routed to monitor mode */
+ new_mode = ARM_CPU_MODE_MON;
+ }
offset = 4;
break;
case EXCP_SMC:
--
1.8.3.2
- Re: [Qemu-devel] [PATCH v10 01/26] target-arm: extend async excp masking, (continued)
- [Qemu-devel] [PATCH v10 03/26] target-arm: add banked register accessors, Greg Bellows, 2014/11/06
- [Qemu-devel] [PATCH v10 02/26] target-arm: add async excp target_el function, Greg Bellows, 2014/11/06
- [Qemu-devel] [PATCH v10 04/26] target-arm: add non-secure Translation Block flag, Greg Bellows, 2014/11/06
- [Qemu-devel] [PATCH v10 05/26] target-arm: add CPREG secure state support, Greg Bellows, 2014/11/06
- [Qemu-devel] [PATCH v10 06/26] target-arm: add secure state bit to CPREG hash, Greg Bellows, 2014/11/06
- [Qemu-devel] [PATCH v10 07/26] target-arm: insert AArch32 cpregs twice into hashtable, Greg Bellows, 2014/11/06
- [Qemu-devel] [PATCH v10 08/26] target-arm: move AArch32 SCR into security reglist, Greg Bellows, 2014/11/06
- [Qemu-devel] [PATCH v10 09/26] target-arm: implement IRQ/FIQ routing to Monitor mode,
Greg Bellows <=
- [Qemu-devel] [PATCH v10 10/26] target-arm: add NSACR register, Greg Bellows, 2014/11/06
- [Qemu-devel] [PATCH v10 11/26] target-arm: add SDER definition, Greg Bellows, 2014/11/06
- [Qemu-devel] [PATCH v10 12/26] target-arm: add MVBAR support, Greg Bellows, 2014/11/06
- [Qemu-devel] [PATCH v10 13/26] target-arm: add SCTLR_EL3 and make SCTLR banked, Greg Bellows, 2014/11/06
- [Qemu-devel] [PATCH v10 14/26] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI, Greg Bellows, 2014/11/06
- [Qemu-devel] [PATCH v10 15/26] target-arm: make CSSELR banked, Greg Bellows, 2014/11/06
- [Qemu-devel] [PATCH v10 16/26] target-arm: make TTBR0/1 banked, Greg Bellows, 2014/11/06