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[Qemu-devel] [PATCH v9 16/26] target-arm: make TTBR0/1 banked
From: |
Greg Bellows |
Subject: |
[Qemu-devel] [PATCH v9 16/26] target-arm: make TTBR0/1 banked |
Date: |
Wed, 5 Nov 2014 17:23:03 -0600 |
From: Fabian Aggeler <address@hidden>
Adds secure and non-secure bank register suport for TTBR0 and TTBR1.
Changes include adding secure and non-secure instances of ttbr0 and ttbr1 as
well as a CP register definition for TTBR0_EL3. Added a union containing
both EL based array fields and secure and non-secure fields mapped to them.
Updated accesses to use A32_BANKED_CURRENT_REG_GET macro.
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
---
v8 -> v9
- Fixed naming of TTBR0/1 and defined with opc0 instead of cp
- Removed get_phys_addr_lpae() AArch64 EL3 support.
- Remove stray whitespace change in pxa2xx.c
v5 -> v6
- Changed _el field variants to be array based
- Merged TTBR# and TTBR#_EL1 reginfo entries
- Globally replace Aarch# with AArch#
---
hw/arm/pxa2xx.c | 2 +-
target-arm/cpu.h | 20 ++++++++++++++++++--
target-arm/helper.c | 37 +++++++++++++++++++++++++------------
3 files changed, 44 insertions(+), 15 deletions(-)
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index 11d51af..2b00b59 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -275,7 +275,7 @@ static void pxa2xx_pwrmode_write(CPUARMState *env, const
ARMCPRegInfo *ri,
s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I;
s->cpu->env.cp15.sctlr_ns = 0;
s->cpu->env.cp15.c1_coproc = 0;
- s->cpu->env.cp15.ttbr0_el1 = 0;
+ s->cpu->env.cp15.ttbr0_el[1] = 0;
s->cpu->env.cp15.c3 = 0;
s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 6996f7c..df761b4 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -199,8 +199,24 @@ typedef struct CPUARMState {
uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
uint64_t sder; /* Secure debug enable register. */
uint32_t nsacr; /* Non-secure access control register. */
- uint64_t ttbr0_el1; /* MMU translation table base 0. */
- uint64_t ttbr1_el1; /* MMU translation table base 1. */
+ union { /* MMU translation table base 0. */
+ struct {
+ uint64_t _unused_ttbr0_0;
+ uint64_t ttbr0_ns;
+ uint64_t _unused_ttbr0_1;
+ uint64_t ttbr0_s;
+ };
+ uint64_t ttbr0_el[4];
+ };
+ union { /* MMU translation table base 1. */
+ struct {
+ uint64_t _unused_ttbr1_0;
+ uint64_t ttbr1_ns;
+ uint64_t _unused_ttbr1_1;
+ uint64_t ttbr1_s;
+ };
+ uint64_t ttbr1_el[4];
+ };
uint64_t c2_control; /* MMU translation table base control. */
uint32_t c2_mask; /* MMU translation table base selection mask. */
uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 6f48291..1e478a1 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1646,13 +1646,15 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
.access = PL1_RW,
.fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
{ .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
- .writefn = vmsa_ttbr_write, .resetvalue = 0 },
+ .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
+ .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
+ .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
+ offsetof(CPUARMState, cp15.ttbr0_ns) } },
{ .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
- .writefn = vmsa_ttbr_write, .resetvalue = 0 },
+ .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
+ .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
+ .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
+ offsetof(CPUARMState, cp15.ttbr1_ns) } },
{ .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
.access = PL1_RW, .writefn = vmsa_tcr_el1_write,
@@ -1883,11 +1885,13 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, cp15.par_el1), .resetvalue = 0 },
{ .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
.access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
- .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
+ .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
+ offsetof(CPUARMState, cp15.ttbr0_ns) },
.writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
{ .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
.access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
- .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
+ .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
+ offsetof(CPUARMState, cp15.ttbr1_ns) },
.writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
REGINFO_SENTINEL
};
@@ -2341,6 +2345,10 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
.access = PL3_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
.fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]) },
+ { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
+ .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
+ .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
{ .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
.type = ARM_CP_NO_MIGRATE,
.opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
@@ -4443,18 +4451,23 @@ static inline int check_ap(CPUARMState *env, int ap,
int domain_prot,
static bool get_level1_table_address(CPUARMState *env, uint32_t *table,
uint32_t address)
{
+ /* We only get here if EL1 is running in AArch32. If EL3 is running in
+ * AArch32 there is a secure and non-secure instance of the translation
+ * table registers.
+ */
if (address & env->cp15.c2_mask) {
if ((env->cp15.c2_control & TTBCR_PD1)) {
/* Translation table walk disabled for TTBR1 */
return false;
}
- *table = env->cp15.ttbr1_el1 & 0xffffc000;
+ *table = A32_BANKED_CURRENT_REG_GET(env, ttbr1) & 0xffffc000;
} else {
if ((env->cp15.c2_control & TTBCR_PD0)) {
/* Translation table walk disabled for TTBR0 */
return false;
}
- *table = env->cp15.ttbr0_el1 & env->cp15.c2_base_mask;
+ *table = A32_BANKED_CURRENT_REG_GET(env, ttbr0) &
+ env->cp15.c2_base_mask;
}
*table |= (address >> 18) & 0x3ffc;
return true;
@@ -4759,7 +4772,7 @@ static int get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
* we will always flush the TLB any time the ASID is changed).
*/
if (ttbr_select == 0) {
- ttbr = env->cp15.ttbr0_el1;
+ ttbr = A32_BANKED_CURRENT_REG_GET(env, ttbr0);
epd = extract32(env->cp15.c2_control, 7, 1);
tsz = t0sz;
@@ -4771,7 +4784,7 @@ static int get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
granule_sz = 11;
}
} else {
- ttbr = env->cp15.ttbr1_el1;
+ ttbr = A32_BANKED_CURRENT_REG_GET(env, ttbr1);
epd = extract32(env->cp15.c2_control, 23, 1);
tsz = t1sz;
--
1.8.3.2
- [Qemu-devel] [PATCH v9 06/26] target-arm: add secure state bit to CPREG hash, (continued)
- [Qemu-devel] [PATCH v9 06/26] target-arm: add secure state bit to CPREG hash, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 08/26] target-arm: move AArch32 SCR into security reglist, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 07/26] target-arm: insert AArch32 cpregs twice into hashtable, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 09/26] target-arm: implement IRQ/FIQ routing to Monitor mode, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 10/26] target-arm: add NSACR register, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 11/26] target-arm: add SDER definition, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 12/26] target-arm: add MVBAR support, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 13/26] target-arm: add SCTLR_EL3 and make SCTLR banked, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 14/26] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 15/26] target-arm: make CSSELR banked, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 16/26] target-arm: make TTBR0/1 banked,
Greg Bellows <=
- [Qemu-devel] [PATCH v9 17/26] target-arm: make TTBCR banked, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 18/26] target-arm: make DACR banked, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 19/26] target-arm: make IFSR banked, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 20/26] target-arm: make DFSR banked, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 21/26] target-arm: make IFAR/DFAR banked, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 22/26] target-arm: make PAR banked, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 23/26] target-arm: make VBAR banked, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 24/26] target-arm: make c13 cp regs banked (FCSEIDR, ...), Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 25/26] target-arm: make MAIR0/1 banked, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 26/26] target-arm: add cpu feature EL3 to CPUs with Security Extensions, Greg Bellows, 2014/11/05