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[Qemu-devel] [PATCH v9 00/26] target-arm: add Security Extensions for CP
From: |
Greg Bellows |
Subject: |
[Qemu-devel] [PATCH v9 00/26] target-arm: add Security Extensions for CPUs |
Date: |
Wed, 5 Nov 2014 17:22:47 -0600 |
Version 9 of the ARM processor security extension (TrustZone) support. This
patchset includes changes to support the processor security extensions
on ARMv7 aarch32 with hooks for later enabling v8 aarch64/32.
Summary of changes from v8 -> v9
- Squashed patch 18 into 17
- Reverted async unmask table fix
- Fixed EL table values
- Removed ARM_CP_SECSTATE_TEST macro
- Updated cpreg hashing and macro arg order so secstate follows is64
- Fixed issuese in add_cpreg_to_hash()
- Reowrked define_one_arm_cp_reg_with_opaque() secure case handling
- Cleaned up CP reg definitions
- Added SDER32_EL2, DACR32_EL2, & IFSR32_EL2 defs
- Removed v8 check in arm_cpu_reset()
- Rearranged cpsr_write() so mask filtering occurs before mode switch
- Added TCR CP reg struct and usage
- Broke up CONTEXTIDR and FCSEIDR CP reg defs into secure/non-secure instances.
- Added missing MAIR endianness support
- Fixed comments
Fabian Aggeler (19):
target-arm: add banked register accessors
target-arm: add CPREG secure state support
target-arm: insert AArch32 cpregs twice into hashtable
target-arm: move AArch32 SCR into security reglist
target-arm: implement IRQ/FIQ routing to Monitor mode
target-arm: add NSACR register
target-arm: add MVBAR support
target-arm: add SCTLR_EL3 and make SCTLR banked
target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI
target-arm: make CSSELR banked
target-arm: make TTBR0/1 banked
target-arm: make TTBCR banked
target-arm: make DACR banked
target-arm: make IFSR banked
target-arm: make DFSR banked
target-arm: make IFAR/DFAR banked
target-arm: make PAR banked
target-arm: make c13 cp regs banked (FCSEIDR, ...)
target-arm: add cpu feature EL3 to CPUs with Security Extensions
Greg Bellows (6):
target-arm: extend async excp masking
target-arm: add async excp target_el function
target-arm: add secure state bit to CPREG hash
target-arm: add SDER definition
target-arm: make VBAR banked
target-arm: make MAIR0/1 banked
Sergey Fedorov (1):
target-arm: add non-secure Translation Block flag
hw/arm/pxa2xx.c | 6 +-
linux-user/aarch64/target_cpu.h | 2 +-
linux-user/arm/target_cpu.h | 2 +-
linux-user/main.c | 2 +-
target-arm/cpu.c | 14 +-
target-arm/cpu.h | 377 ++++++++++++++++++----
target-arm/helper.c | 682 ++++++++++++++++++++++++++++++----------
target-arm/internals.h | 6 +-
target-arm/op_helper.c | 4 +-
target-arm/translate.c | 15 +-
target-arm/translate.h | 1 +
11 files changed, 869 insertions(+), 242 deletions(-)
--
1.8.3.2
- [Qemu-devel] [PATCH v9 00/26] target-arm: add Security Extensions for CPUs,
Greg Bellows <=
- [Qemu-devel] [PATCH v9 01/26] target-arm: extend async excp masking, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 03/26] target-arm: add banked register accessors, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 04/26] target-arm: add non-secure Translation Block flag, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 02/26] target-arm: add async excp target_el function, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 05/26] target-arm: add CPREG secure state support, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 06/26] target-arm: add secure state bit to CPREG hash, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 08/26] target-arm: move AArch32 SCR into security reglist, Greg Bellows, 2014/11/05
- [Qemu-devel] [PATCH v9 07/26] target-arm: insert AArch32 cpregs twice into hashtable, Greg Bellows, 2014/11/05