Re: [Qemu-devel] State of ARM FIQ in Qemu

[Greg Bellows]

On 3 November 2014 10:22, Tim Sander <address@hidden> wrote:

Hi Greg

Thanks for your fast reply.
> I am still in the process of getting the security extension portion of the
> GIC patches fully up and running.  By the sounds of your use, it sounds
> like you just want FIQ support not necessarily secure GIC support.  Would
> this be correct?
Yes. More elaborate i am working on a modified cortexa9 versatile express,
where i added my virtual test hardware.

> I recently sent out an updated set of patches for review that contain GIC
> interrupt grouping and FIQ enablement along with secure extension
> infrastructure.  If interested, you can find the patches here:
>
> http://lists.nongnu.org/archive/html/qemu-devel/2014-10/msg03921.html
>
> Alternatively, it sounds like you have access to the Linaro GIT repos, in
> which case you can use the following repo/branch that contains the same
> patches.  It is based on fairly recent upstream bits.
>
> repo: git://git.linaro.org/people/greg.bellows/qemu.git
> branch: tzqemu_gic_v2
>
> If you don't need the security extensions, then you shouldn't need to do
> anything to the code to get FIQ support on vexpress-a9/15 or virt machines.
Ok but i think i see a RAZ codepath in qemu when accessing the gic registers
configuring the interrupt group. 

> Please let me know if you have any further questions or issues.

I have the problem that the secure_extn property is not set and i have not
figured out a way to set these.  The corresponding code is a slighly modified
vexpress_common_init in hw/arm/vexpress.c.:519.

I guess setting the property would be done by
qdev_prop_set_bool(dev,"security_extn",TRUE);
but i fail to find the "dev" from the GIC i could use as argument.

Attached is also a snipped from a debugger run verifing that its indeed
s->security-extn which is missing.

Ah... Yes, using A9 (GICv1) which means you don't have grouping without the security extensions.  I tried enabling the security extensions and things hung, however, I was able to boot A9 Linux and use FIQs with the following change:

 diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c

index c09358c..813ae92 100644

--- a/hw/cpu/a9mpcore.c

+++ b/hw/cpu/a9mpcore.c

@@ -29,6 +29,8 @@ static void a9mp_priv_initfn(Object *obj)

 

     object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);

     qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());

+    qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);

 

     object_initialize(&s->gtimer, sizeof(s->gtimer), TYPE_A9_GTIMER);

     qdev_set_parent_bus(DEVICE(&s->gtimer), sysbus_get_default());

 

This may be at least a workaround for you while I figure out where the security configuration gets hung-up.  Can you give this a try and see if you can make progress?

The security extensions aspect of the code is fairly untested as I still need secure address space support, so there may be glitches when security is enabled.

Best regards
Tim

Breakpoint 3, gic_dist_writeb (opaque=0x555556368a80, offset=136, value=0) at
hw/intc/arm_gic.c:820
820             } else if (offset >= 0x80) {
(gdb) list
815                     s->enabled = (value & 0x1);
816                     DPRINTF("Distribution %sabled\n", s->enabled ? "En" :
"Dis");
817                 }
818             } else if (offset < 4) {
819                 /* ignored.  */
820             } else if (offset >= 0x80) {
821                 /* Interrupt Group Registers
822                  *
823                  * For GIC with Security Extn and Non-secure access RAZ/WI
824                  * For GICv1 without Security Extn RAZ/WI
(gdb) n
826                 if (!(s->security_extn && ns_access()) &&
(gdb) n
828                                 || s->revision == 2)) {
(gdb) n
999         gic_update(s);
(gdb) print s->security_extn
$2 = false