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[Qemu-devel] [PATCH v3 12/15] target-mips: CP0_Status.CU0 no longer allo
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PATCH v3 12/15] target-mips: CP0_Status.CU0 no longer allows the user to access CP0 |
Date: |
Fri, 24 Oct 2014 13:42:26 +0100 |
Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>
---
target-mips/cpu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 6367d8c..3b975eb 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -790,7 +790,8 @@ static inline void compute_hflags(CPUMIPSState *env)
}
}
#endif
- if ((env->CP0_Status & (1 << CP0St_CU0)) ||
+ if (((env->CP0_Status & (1 << CP0St_CU0)) &&
+ !(env->insn_flags & ISA_MIPS32R6)) ||
!(env->hflags & MIPS_HFLAG_KSU)) {
env->hflags |= MIPS_HFLAG_CP0;
}
--
2.1.0
- Re: [Qemu-devel] [PATCH v3 02/15] softmmu: provide softmmu access type enum, (continued)
- [Qemu-devel] [PATCH v3 03/15] target-mips: distinguish between data load and instruction fetch, Leon Alrae, 2014/10/24
- [Qemu-devel] [PATCH v3 04/15] target-mips: add RI and XI fields to TLB entry, Leon Alrae, 2014/10/24
- [Qemu-devel] [PATCH v3 05/15] target-mips: update PageGrain and m{t, f}c0 EntryLo{0, 1}, Leon Alrae, 2014/10/24
- [Qemu-devel] [PATCH v3 07/15] target-mips: add TLBINV support, Leon Alrae, 2014/10/24
- [Qemu-devel] [PATCH v3 06/15] target-mips: add new Read-Inhibit and Execute-Inhibit exceptions, Leon Alrae, 2014/10/24
- [Qemu-devel] [PATCH v3 08/15] target-mips: add BadInstr and BadInstrP support, Leon Alrae, 2014/10/24
- [Qemu-devel] [PATCH v3 09/15] target-mips: update cpu_save/cpu_load to support new registers, Leon Alrae, 2014/10/24
- [Qemu-devel] [PATCH v3 10/15] target-mips: add Config5.SBRI, Leon Alrae, 2014/10/24
- [Qemu-devel] [PATCH v3 12/15] target-mips: CP0_Status.CU0 no longer allows the user to access CP0,
Leon Alrae <=
- [Qemu-devel] [PATCH v3 11/15] target-mips: implement forbidden slot, Leon Alrae, 2014/10/24
- [Qemu-devel] [PATCH v3 13/15] target-mips: add restrictions for possible values in registers, Leon Alrae, 2014/10/24
- [Qemu-devel] [PATCH v3 15/15] target-mips: enable features in MIPS64R6-generic CPU, Leon Alrae, 2014/10/24
- [Qemu-devel] [PATCH v3 14/15] target-mips: correctly handle access to unimplemented CP0 register, Leon Alrae, 2014/10/24