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[Qemu-devel] [PULL 15/23] target-arm: Correct sense of the DCZID DZP bit
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 15/23] target-arm: Correct sense of the DCZID DZP bit |
Date: |
Fri, 24 Oct 2014 12:37:21 +0100 |
The DZP bit in the DCZID system register should be set if
the control bits which prohibit use of the DC ZVA instruction
have been set (it stands for Data Zero Prohibited). However
we had the sense of the test inverted; fix this so that the
bit reads correctly.
To avoid this regressing the behaviour of the user-mode
emulator, we must set the DZE bit in the SCTLR for that
config so that userspace continues to see DZP as zero (it
was getting the correct result by accident previously).
Reported-by: Christopher Covington <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Christopher Covington <address@hidden>
Message-id: address@hidden
---
target-arm/cpu.c | 4 ++--
target-arm/helper.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index e837f64..e0b82a6 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -108,8 +108,8 @@ static void arm_cpu_reset(CPUState *s)
env->aarch64 = 1;
#if defined(CONFIG_USER_ONLY)
env->pstate = PSTATE_MODE_EL0t;
- /* Userspace expects access to CTL_EL0 and the cache ops */
- env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI;
+ /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
+ env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
/* and to the FP/Neon instructions */
env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3);
#else
diff --git a/target-arm/helper.c b/target-arm/helper.c
index d837820..53527c2 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2018,7 +2018,7 @@ static uint64_t aa64_dczid_read(CPUARMState *env, const
ARMCPRegInfo *ri)
int dzp_bit = 1 << 4;
/* DZP indicates whether DC ZVA access is allowed */
- if (aa64_zva_access(env, NULL) != CP_ACCESS_OK) {
+ if (aa64_zva_access(env, NULL) == CP_ACCESS_OK) {
dzp_bit = 0;
}
return cpu->dcz_blocksize | dzp_bit;
--
1.9.1
- [Qemu-devel] [PULL 00/23] target-arm queue, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 22/23] target-arm: make arm_current_el() return EL3, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 16/23] target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any", Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 15/23] target-arm: Correct sense of the DCZID DZP bit,
Peter Maydell <=
- [Qemu-devel] [PULL 14/23] arm/virt: enable PSCI emulation support for system emulation, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 11/23] target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpers, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 12/23] target-arm: Add support for A32 and T32 HVC and SMC insns, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 08/23] target-arm: add powered off cpu state, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 09/23] target-arm: do not set do_interrupt handlers for ARM and AArch64 user modes, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 10/23] target-arm: add missing PSCI constants needed for PSCI emulation, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 07/23] omap_gpmc.c: Remove duplicate assignment, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 17/23] target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 18/23] target-arm: increase arrays of registers R13 & R14, Peter Maydell, 2014/10/24
- [Qemu-devel] [PULL 20/23] target-arm: reject switching to monitor mode, Peter Maydell, 2014/10/24