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[Qemu-devel] [PATCH v7 06/32] target-arm: A32: Emulate the SMC instructi
From: |
Greg Bellows |
Subject: |
[Qemu-devel] [PATCH v7 06/32] target-arm: A32: Emulate the SMC instruction |
Date: |
Tue, 21 Oct 2014 11:55:18 -0500 |
From: Fabian Aggeler <address@hidden>
Implements SMC instruction in AArch32 using the A32 syndrome. When executing
SMC instruction from monitor CPU mode SCR.NS bit is reset.
Signed-off-by: Sergey Fedorov <address@hidden>
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
==========
v5 -> v6
- Fixed PC offsetting for presmc
- Removed extraneous semi-colon
- Fixed merge issue
v4 -> v5
- Merge pre_smc upstream changes and incorporated ss_advance
Signed-off-by: Greg Bellows <address@hidden>
---
target-arm/helper.c | 11 +++++++++++
target-arm/op_helper.c | 3 +--
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 033b18f..38d9f7b 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -4091,6 +4091,12 @@ void arm_cpu_do_interrupt(CPUState *cs)
mask = CPSR_A | CPSR_I | CPSR_F;
offset = 4;
break;
+ case EXCP_SMC:
+ new_mode = ARM_CPU_MODE_MON;
+ addr = 0x08;
+ mask = CPSR_A | CPSR_I | CPSR_F;
+ offset = 0;
+ break;
default:
cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
return; /* Never happens. Keep compiler happy. */
@@ -4109,6 +4115,11 @@ void arm_cpu_do_interrupt(CPUState *cs)
*/
addr += env->cp15.vbar_el[1];
}
+
+ if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
+ env->cp15.scr_el3 &= ~SCR_NS;
+ }
+
switch_mode (env, new_mode);
/* For exceptions taken to AArch32 we must clear the SS bit in both
* PSTATE and in the old-state value we save to SPSR_<mode>, so zero it
now.
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 6cc3387..62012c3 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -429,8 +429,7 @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
{
ARMCPU *cpu = arm_env_get_cpu(env);
int cur_el = arm_current_el(env);
- /* FIXME: Use real secure state. */
- bool secure = false;
+ bool secure = arm_is_secure(env);
bool smd = env->cp15.scr_el3 & SCR_SMD;
/* On ARMv8 AArch32, SMD only applies to NS state.
* On ARMv7 SMD only applies to NS state and only if EL2 is available.
--
1.8.3.2
- Re: [Qemu-devel] [PATCH v7 08/32] target-arm: add async excp target_el function, (continued)
[Qemu-devel] [PATCH v7 09/32] target-arm: add banked register accessors, Greg Bellows, 2014/10/21
[Qemu-devel] [PATCH v7 06/32] target-arm: A32: Emulate the SMC instruction,
Greg Bellows <=
[Qemu-devel] [PATCH v7 04/32] target-arm: rename arm_current_pl to arm_current_el, Greg Bellows, 2014/10/21
[Qemu-devel] [PATCH v7 11/32] target-arm: add CPREG secure state support, Greg Bellows, 2014/10/21
[Qemu-devel] [PATCH v7 13/32] target-arm: insert AArch32 cpregs twice into hashtable, Greg Bellows, 2014/10/21
[Qemu-devel] [PATCH v7 14/32] target-arm: move AArch32 SCR into security reglist, Greg Bellows, 2014/10/21
[Qemu-devel] [PATCH v7 15/32] target-arm: implement IRQ/FIQ routing to Monitor mode, Greg Bellows, 2014/10/21
[Qemu-devel] [PATCH v7 16/32] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI, Greg Bellows, 2014/10/21
[Qemu-devel] [PATCH v7 17/32] target-arm: add NSACR register, Greg Bellows, 2014/10/21
[Qemu-devel] [PATCH v7 19/32] target-arm: add MVBAR support, Greg Bellows, 2014/10/21