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[Qemu-devel] [PATCH v5 29/33] target-arm: make VBAR banked
From: |
Greg Bellows |
Subject: |
[Qemu-devel] [PATCH v5 29/33] target-arm: make VBAR banked |
Date: |
Tue, 30 Sep 2014 16:49:41 -0500 |
From: Fabian Aggeler <address@hidden>
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
VBAR has a secure and a non-secure instance, which are mapped to
VBAR_EL1 and VBAR_EL3.
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
----------------
v3 -> v4
- Fix vbar union/structure definition
- Revert back to array-based vbar definition combined with v7 naming
---
target-arm/cpu.h | 10 +++++++++-
target-arm/helper.c | 13 +++++++++----
2 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 4b70530..1fa9e0d 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -311,7 +311,15 @@ typedef struct CPUARMState {
uint32_t c9_pmuserenr; /* perf monitor user enable */
uint32_t c9_pminten; /* perf monitor interrupt enables */
uint64_t mair_el1;
- uint64_t vbar_el[4]; /* vector base address register */
+ union { /* vector base address register */
+ struct {
+ uint64_t _unused_vbar;
+ uint64_t vbar_ns;
+ uint64_t hvbar;
+ uint64_t vbar_s;
+ };
+ uint64_t vbar_el[4];
+ };
uint64_t mvbar; /* (monitor) vector base address register */
uint32_t c13_fcse; /* FCSE PID. */
uint64_t contextidr_el1; /* Context ID. */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 2b0918f..8543813 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -918,9 +918,9 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.resetvalue = 0, .writefn = pmintenclr_write, },
{ .name = "VBAR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW, .writefn = vbar_write,
- .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]),
- .resetvalue = 0 },
+ .access = PL1_RW, .writefn = vbar_write, .resetvalue = 0,
+ .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
+ offsetof(CPUARMState, cp15.vbar_ns) } },
{ .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
.access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
@@ -2313,6 +2313,11 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
.type = ARM_CP_NO_MIGRATE,
.access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
+ { .name = "VBAR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 0,
+ .access = PL1_RW, .writefn = vbar_write,
+ .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]),
+ .resetvalue = 0 },
{ .name = "CSSELR_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
.access = PL1_RW, .writefn = csselr_write, .resetvalue = 0,
@@ -4451,7 +4456,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
* This register is only followed in non-monitor mode, and is banked.
* Note: only bits 31:5 are valid.
*/
- addr += env->cp15.vbar_el[1];
+ addr += A32_BANKED_CURRENT_REG_GET(env, vbar);
}
if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
--
1.8.3.2
- [Qemu-devel] [PATCH v5 19/33] target-arm: add SCTLR_EL3 and make SCTLR banked, (continued)
- [Qemu-devel] [PATCH v5 19/33] target-arm: add SCTLR_EL3 and make SCTLR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 18/33] target-arm: add MVBAR support, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 21/33] target-arm: add TTBR0_EL3 and make TTBR0/1 banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 24/33] target-arm: make DACR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 23/33] target-arm: make c2_mask and c2_base_mask banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 27/33] target-arm: make IFAR/DFAR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 30/33] target-arm: make MAIR0/1 banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 28/33] target-arm: make PAR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 33/33] target-arm: add cpu feature EL3 to CPUs with Security Extensions, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 25/33] target-arm: make IFSR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 29/33] target-arm: make VBAR banked,
Greg Bellows <=
- [Qemu-devel] [PATCH v5 26/33] target-arm: make DFSR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 32/33] target-arm: add GDB scr register, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 22/33] target-arm: add TCR_EL3 and make TTBCR banked, Greg Bellows, 2014/09/30
- [Qemu-devel] [PATCH v5 31/33] target-arm: make c13 cp regs banked (FCSEIDR, ...), Greg Bellows, 2014/09/30