Re: [Qemu-devel] [PATCH 2/5] target-tricore: Add instructions of ABS, ABSB opcode format

[Richard Henderson]

On 09/27/2014 07:58 AM, Bastian Koppelmann wrote:
 +    env->gpr_a[2] = cpu_ldl_data(env, ea+8);
> +    env->gpr_a[3] = cpu_ldl_data(env, ea+12);
> +    env->gpr_d[0]  = cpu_ldl_data(env, ea+16);
> +    env->gpr_d[1]  = cpu_ldl_data(env, ea+20);
> +    env->gpr_d[2] = cpu_ldl_data(env, ea+24);

Watch the extra spaces.

> +static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext 
> *ctx)
> +{
> +    TCGv_i64 temp = tcg_temp_new_i64();
> +
> +    tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEQ);
> +    /* write back to two 32 bit regs */
> +    tcg_gen_trunc_i64_i32(rl, temp);
> +    tcg_gen_shri_i64(temp, temp, 32);
> +    tcg_gen_trunc_i64_i32(rh, temp);

tcg_gen_extr_i64_i32(rl, rh, temp)

> +/* ABSB-format */
> +    case OPC1_32_ABSB_ST_T:
> +        address = MASK_OP_ABS_OFF18(ctx->opcode);
> +        int8_t b = MASK_OP_ABSB_B(ctx->opcode);
> +        int32_t bpos = MASK_OP_ABSB_BPOS(ctx->opcode);

You're not supposed to be relying on c99 mixed code and declarations.


r~