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[Qemu-devel] [PATCH v7 08/11] target-arm: Add a Hypervisor Trap exceptio
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v7 08/11] target-arm: Add a Hypervisor Trap exception type |
Date: |
Fri, 26 Sep 2014 18:08:31 +1000 |
From: "Edgar E. Iglesias" <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target-arm/cpu.h | 1 +
target-arm/helper-a64.c | 1 +
target-arm/helper.c | 1 +
target-arm/internals.h | 1 +
4 files changed, 4 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index b553f3d..ef933e8 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -52,6 +52,7 @@
#define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
#define EXCP_STREX 10
#define EXCP_HVC 11 /* HyperVisor Call */
+#define EXCP_HYP_TRAP 12
#define ARMV7M_EXCP_RESET 1
#define ARMV7M_EXCP_NMI 2
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index 4e6ca26..0a7c155 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -477,6 +477,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
case EXCP_UDEF:
case EXCP_SWI:
case EXCP_HVC:
+ case EXCP_HYP_TRAP:
env->cp15.esr_el[new_el] = env->exception.syndrome;
break;
case EXCP_IRQ:
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 9e7d0f6..802d779 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3664,6 +3664,7 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned
int excp_idx)
switch (excp_idx) {
case EXCP_HVC:
+ case EXCP_HYP_TRAP:
target_el = 2;
break;
default:
diff --git a/target-arm/internals.h b/target-arm/internals.h
index afcc4e0..4fbb136 100644
--- a/target-arm/internals.h
+++ b/target-arm/internals.h
@@ -54,6 +54,7 @@ static const char * const excnames[] = {
[EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
[EXCP_STREX] = "QEMU intercept of STREX",
[EXCP_HVC] = "Hypervisor Call",
+ [EXCP_HYP_TRAP] = "Hypervisor Trap",
};
static inline void arm_log_exception(int idx)
--
1.9.1
- [Qemu-devel] [PATCH v7 00/11] target-arm: Parts of the AArch64 EL2/3 exception model, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 01/11] target-arm: Add HCR_EL2, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 02/11] target-arm: Add SCR_EL3, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 04/11] target-arm: Break out exception masking to a separate func, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 05/11] target-arm: Don't take interrupts targeting lower ELs, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 06/11] target-arm: A64: Correct updates to FAR and ESR on exceptions, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 07/11] target-arm: A64: Emulate the HVC insn, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 08/11] target-arm: Add a Hypervisor Trap exception type,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v7 10/11] target-arm: Add IRQ and FIQ routing to EL2 and 3, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 11/11] target-arm: Add support for VIRQ and VFIQ, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 03/11] target-arm: A64: Refactor aarch64_cpu_do_interrupt, Edgar E. Iglesias, 2014/09/26
- [Qemu-devel] [PATCH v7 09/11] target-arm: A64: Emulate the SMC insn, Edgar E. Iglesias, 2014/09/26
- Re: [Qemu-devel] [PATCH v7 00/11] target-arm: Parts of the AArch64 EL2/3 exception model, Peter Maydell, 2014/09/26