Re: [Qemu-devel] [Patch v1 2/8] stm32f205_USART: Add the stm32f205 USART Controller

[Alistair Francis]

On Tue, Sep 16, 2014 at 1:11 AM, Peter Crosthwaite
<address@hidden> wrote:
> On Sun, Sep 14, 2014 at 6:18 PM, Alistair Francis <address@hidden> wrote:
>> This patch adds the stm32f205 USART controller
>> (UART also uses the same controller).
>>
>> Signed-off-by: Alistair Francis <address@hidden>
>> ---
>> Changes from RFC:
>>  - Small changes thanks to Peter C
>>  - USART now implements QEMU blocking functions
>>  - Split the config settings to device level
>>
>>  default-configs/arm-softmmu.mak   |   1 +
>>  hw/char/Makefile.objs             |   1 +
>>  hw/char/stm32f205_usart.c         | 213 
>> ++++++++++++++++++++++++++++++++++++++
>>  include/hw/char/stm32f205_usart.h |  67 ++++++++++++
>>  4 files changed, 282 insertions(+)
>>  create mode 100644 hw/char/stm32f205_usart.c
>>  create mode 100644 include/hw/char/stm32f205_usart.h
>>
>> diff --git a/default-configs/arm-softmmu.mak 
>> b/default-configs/arm-softmmu.mak
>> index cf23b24..422dec0 100644
>> --- a/default-configs/arm-softmmu.mak
>> +++ b/default-configs/arm-softmmu.mak
>> @@ -79,6 +79,7 @@ CONFIG_REALVIEW=y
>>  CONFIG_ZAURUS=y
>>  CONFIG_ZYNQ=y
>>  CONFIG_STM32F205_TIMER=y
>> +CONFIG_STM32F205_USART=y
>>
>>  CONFIG_VERSATILE_PCI=y
>>  CONFIG_VERSATILE_I2C=y
>> diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs
>> index 317385d..c7b3ce4 100644
>> --- a/hw/char/Makefile.objs
>> +++ b/hw/char/Makefile.objs
>> @@ -15,6 +15,7 @@ obj-$(CONFIG_OMAP) += omap_uart.o
>>  obj-$(CONFIG_SH4) += sh_serial.o
>>  obj-$(CONFIG_PSERIES) += spapr_vty.o
>>  obj-$(CONFIG_DIGIC) += digic-uart.o
>> +obj-$(CONFIG_STM32F205_USART) += stm32f205_usart.o
>>
>>  common-obj-$(CONFIG_ETRAXFS) += etraxfs_ser.o
>>  common-obj-$(CONFIG_ISA_DEBUG) += debugcon.o
>> diff --git a/hw/char/stm32f205_usart.c b/hw/char/stm32f205_usart.c
>> new file mode 100644
>> index 0000000..1274e69
>> --- /dev/null
>> +++ b/hw/char/stm32f205_usart.c
>> @@ -0,0 +1,213 @@
>> +/*
>> + * STM32F205 USART
>> + *
>> + * Copyright (c) 2014 Alistair Francis <address@hidden>
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a 
>> copy
>> + * of this software and associated documentation files (the "Software"), to 
>> deal
>> + * in the Software without restriction, including without limitation the 
>> rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be included 
>> in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 
>> OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 
>> OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
>> FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>> + * THE SOFTWARE.
>> + */
>> +
>> +#include "hw/char/stm32f205_usart.h"
>> +
>> +#ifndef STM_USART_ERR_DEBUG
>> +#define STM_USART_ERR_DEBUG 0
>> +#endif
>> +
>> +#define DB_PRINT_L(lvl, fmt, args...) do { \
>> +    if (STM_USART_ERR_DEBUG >= lvl) { \
>> +        qemu_log("stm32f205_usart: %s:" fmt, __func__, ## args); \
>> +    } \
>> +} while (0);
>> +
>> +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
>> +
>> +static int stm32f205_usart_can_receive(void *opaque)
>> +{
>> +    STM32f205UsartState *s = opaque;
>> +
>> +    if (s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE &&
>
> So this is still gating based on the master enable. I think these
> first two terms in the && need to be dropped ...
>
>> +        !(s->usart_sr & USART_SR_RXNE)) {
>> +        return 1;
>> +    }
>> +
>> +    return 0;
>> +}
>> +
>> +static void stm32f205_usart_receive(void *opaque, const uint8_t *buf, int 
>> size)
>> +{
>> +    STM32f205UsartState *s = opaque;
>> +
>> +    s->usart_dr = *buf;
>> +
>
> and here:
>
> if (!s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE) {
>    return; /* not enabled - drop chars */
> }
>
> This means the UART will drop chars when its disabled, which would be
> consistent with real HW (there is no buffering when the sender sends
> chars to a disabled UART).

This makes sense, will fix it

Thanks,

Alistair

>
>> +    s->usart_sr |= USART_SR_RXNE;
>> +
>> +    if (s->usart_cr1 & USART_CR1_RXNEIE) {
>> +        qemu_set_irq(s->irq, 1);
>> +    }
>> +
>> +    DB_PRINT("Receiving: %c\n", s->usart_dr);
>> +}
>> +
>> +static void stm32f205_usart_reset(DeviceState *dev)
>> +{
>> +    STM32f205UsartState *s = STM32F205_USART(dev);
>> +
>> +    s->usart_sr = 0x00C00000;
>
> Just define a macro for this field and set it for self documentation.
>
>> +    s->usart_dr = 0x00000000;
>> +    s->usart_brr = 0x00000000;
>> +    s->usart_cr1 = 0x00000000;
>> +    s->usart_cr2 = 0x00000000;
>> +    s->usart_cr3 = 0x00000000;
>> +    s->usart_gtpr = 0x00000000;
>> +}
>> +
>> +static uint64_t stm32f205_usart_read(void *opaque, hwaddr addr,
>> +                                       unsigned int size)
>> +{
>> +    STM32f205UsartState *s = opaque;
>> +    uint64_t retvalue;
>> +
>> +    DB_PRINT("Read 0x%"HWADDR_PRIx"\n", addr);
>> +
>> +    switch (addr) {
>> +    case USART_SR:
>> +        retvalue = s->usart_sr;
>> +        s->usart_sr &= ~USART_SR_TC;
>> +        if (s->chr) {
>> +            qemu_chr_accept_input(s->chr);
>> +        }
>> +        return retvalue;
>> +    case USART_DR:
>> +        DB_PRINT("Value: 0x%x, %c\n", s->usart_dr, (char) s->usart_dr);
>
> PRIx32 to match type of usart_dr.
>
>> +        s->usart_sr |= USART_SR_TXE;
>> +        s->usart_sr &= ~USART_SR_RXNE;
>> +        return s->usart_dr & 0x3FF;
>> +    case USART_BRR:
>> +        return s->usart_brr;
>> +    case USART_CR1:
>> +        return s->usart_cr1;
>> +    case USART_CR2:
>> +        return s->usart_cr2;
>> +    case USART_CR3:
>> +        return s->usart_cr3;
>> +    case USART_GTPR:
>> +        return s->usart_gtpr;
>> +    default:
>> +        qemu_log_mask(LOG_GUEST_ERROR,
>> +                      "STM32F205_usart_read: Bad offset " \
>> +                      "0x%"HWADDR_PRIx"\n", addr);
>> +        return 0;
>> +    }
>> +
>> +    return 0;
>> +}
>> +
>> +static void stm32f205_usart_write(void *opaque, hwaddr addr,
>> +                       uint64_t val64, unsigned int size)
>> +{
>> +    STM32f205UsartState *s = opaque;
>> +    uint32_t value = val64;
>> +    unsigned char ch;
>> +
>> +    DB_PRINT("Write 0x%x, 0x%"HWADDR_PRIx"\n", value, addr);
>> +
>
> PRIx64 for value.
>
> Regards,
> Peter