Re: [Qemu-devel] [PATCH 03/14] target-ppc: use separate indices for various translation modes

[Richard Henderson]

On 09/16/2014 11:41 AM, Richard Henderson wrote:
>> In practice, only 3 to 7 are---hence my original attempt at using some
>> kind of FIFO caching:
>>
>>    user mode, translation enabled
>>    kernel mode, paging disabled
>>    kernel mode, paging enabled
>>    supervisor mode, paging disabled
>>    supervisor mode, paging enabled
>>
>> Plus perhaps kernel and supervisor mode with only data paging enabled.
>>
>> You could lump together the IR!=0, DR!=0 cases, and flush that one TLB
>> index if the IR/DR pair changes with respect to the last time.  This
>> would use 6 indices.
> 
> I think I would prefer a solution that uses 6 indicies, as will not cause env
> to overflow 64k, and not require that any tcg backends be updated.

... alternately ...

What if instead of having a "mmu_index" for the mmu arrays, we have a pointer
to the "mmu context".  This does imply an extra memory load on the fast path,
but probably not an extra instruction.

With this, we can suddenly afford to have a relatively large number of mmu
contexts, with which we could implement address space numbers for relevant 
targets.

It is, of course, a much larger change, but perhaps it's of larger benefit.


r~