|
From: | Pierre Mallard |
Subject: | Re: [Qemu-devel] [PATCH 0/2] Enabling floating point instruction to 440x5 CPUs |
Date: | Fri, 12 Sep 2014 21:27:02 +0200 |
NIT: It is customary to version your patches so that we can all keep them straight. So "[V2 PATCH 0/2] ...". You can use the --subject-prefix option to git format-patch. I will defer to Alex on whether he wants you to resubmit.On 9/11/2014 2:17 PM, Pierre Mallard wrote:
> This patch series enable floating point instruction in 440x5 CPUs
> which have the capabilities to have optional APU FPU in double precision mode.
>
> 1) Allow fc[tf]id[*] mnemonics for non TARGET_PPC64 with a new insn2 flag
> 2) Create a new 440x5 implementing floating point instructions
>
> Pierre Mallard (2):
> target-ppc : Allow fc[tf]id[*] mnemonics for non TARGET_PPC64
> target-ppc : Add new processor type 440x5wDFPU
>
> target-ppc/cpu-models.c | 3 +++
> target-ppc/cpu.h | 5 ++++-
> target-ppc/fpu_helper.c | 6 ------
> target-ppc/helper.h | 4 +---
> target-ppc/translate.c | 18 +++++++----------
> target-ppc/translate_init.c | 47 ++++++++++++++++++++++++++++++++++++++++---
> 6 files changed, 59 insertions(+), 24 deletions(-)
>
[Prev in Thread] | Current Thread | [Next in Thread] |