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Re: [Qemu-devel] [PATCH target-arm v3 1/1] arm: cortex-a9: Fix cache-lin
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From: |
Peter Maydell |
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Subject: |
Re: [Qemu-devel] [PATCH target-arm v3 1/1] arm: cortex-a9: Fix cache-line size and associativity |
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Date: |
Tue, 19 Aug 2014 14:28:47 +0100 |
On 18 August 2014 08:17, Peter Crosthwaite <address@hidden> wrote:
> For A9, The cache associativity is 4 and the lines size is 32B.
> Self identify in CCSIDR accordingly. Cache size remains at 16k.
>
> QEMU doesn't emulate caches, but we should still report the correct
> cache-line size to the guest. Some guests (like u-boot) complain if
> the cache-line size mismatches a requested flush or invalidate
> operation.
Thanks, applied to target-arm.next. Not sure where the bogus
values originally came from...
-- PMM