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Re: [Qemu-devel] [PULL 17/19] target-i386: Support "invariant tsc" flag

From: chenliang (T)
Subject: Re: [Qemu-devel] [PULL 17/19] target-i386: Support "invariant tsc" flag
Date: Fri, 8 Aug 2014 07:07:59 +0000

We found that value of host cpus tsc are same to echo other when host has 
invariant tsc flag.
But it is not in vm. The problem is that offset of vcpus tsc are not equal. The 
offset is set when
vcpu is created. Is it ok to set same offset? And is it reasonable?

Best regards
Chen Liang

From: Marcelo Tosatti <address@hidden>

Expose "Invariant TSC" flag, if KVM is enabled. From Intel documentation:

17.13.1 Invariant TSC The time stamp counter in newer processors may support an 
enhancement, referred to as invariant TSC. Processor’s support for invariant 
TSC is indicated by CPUID.80000007H:EDX[8].
The invariant TSC will run at a constant rate in all ACPI P-, C-.
and T-states. This is the architectural behavior moving forward. On processors 
with invariant TSC support, the OS may use the TSC for wall clock timer 
services (instead of ACPI or HPET timers). TSC reads are much more efficient 
and do not incur the overhead associated with a ring transition or access to a 
platform resource.

Signed-off-by: Marcelo Tosatti <address@hidden>
[ehabkost: redo feature filtering to use .tcg_features]
[ehabkost: add CPUID_APM_INVTSC macro, add it to .unmigratable_flags]
Signed-off-by: Eduardo Habkost <address@hidden>
Signed-off-by: Andreas Färber <address@hidden>

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