[Qemu-devel] [PATCH 25/28] ahci: add test_pci_enable to ahci-test.

[John Snow]

This adds a test wherein we engage the PCI AHCI
device and ensure that the memory region for the
HBA functionality is now accessible.

Under Q35 environments, additional PCI configuration
is performed to ensure that the HBA functionality
will become usable.

Signed-off-by: John Snow <address@hidden>
---
 tests/ahci-test.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/tests/ahci-test.c b/tests/ahci-test.c
index e0a8f34..7b45064 100644
--- a/tests/ahci-test.c
+++ b/tests/ahci-test.c
@@ -38,6 +38,13 @@
 #include "hw/pci/pci_ids.h"
 #include "hw/pci/pci_regs.h"
 
+/* Test the Q35/ICH9 behavior in preference to AHCI 1.3 behavior */
+#define Q35
+
+#ifndef Q35
+#define AHCI_13_STRICT
+#endif
+
 /* Test-specific defines. */
 #define TEST_IMAGE_SIZE    (64 * 1024 * 1024)
 
@@ -66,6 +73,7 @@ static char tmp_path[] = "/tmp/qtest.XXXXXX";
 
 /*** Function Declarations ***/
 static QPCIDevice *get_ahci_device(void);
+static QPCIDevice *start_ahci_device(QPCIDevice *dev, HBA **hba_base);
 static void free_ahci_device(QPCIDevice *dev);
 static void ahci_test_pci_spec(QPCIDevice *ahci);
 static void ahci_test_pci_caps(QPCIDevice *ahci, uint16_t header,
@@ -174,6 +182,58 @@ static void ahci_shutdown(QPCIDevice *ahci)
     qtest_shutdown();
 }
 
+/*** Logical Device Initialization ***/
+
+/**
+ * Start the PCI device and sanity-check default operation.
+ */
+static void ahci_pci_enable(QPCIDevice *ahci, HBA **hba_base)
+{
+    uint8_t reg;
+
+    start_ahci_device(ahci, hba_base);
+
+#ifdef Q35
+    /* ICH9 has a register at PCI 0x92 that
+     * acts as a master port enabler mask. */
+    reg = qpci_config_readb(ahci, 0x92);
+    reg |= 0x3F;
+    qpci_config_writeb(ahci, 0x92, reg);
+    assert_bit_set(qpci_config_readb(ahci, 0x92), 0x3F);
+#endif
+}
+
+/**
+ * Map BAR5/ABAR, and engage the PCI device.
+ */
+static QPCIDevice *start_ahci_device(QPCIDevice *ahci, HBA **hba_base)
+{
+    uint16_t data;
+
+    /* Map AHCI's ABAR (BAR5) */
+    *hba_base = qpci_iomap(ahci, 5);
+
+    /* turns on pci.cmd.iose, pci.cmd.mse and pci.cmd.bme */
+    qpci_device_enable(ahci);
+
+#ifdef USE_MSI
+    data |= PCI_COMMAND_INTX_DISABLE;
+    qpci_config_writew(ahci, PCI_COMMAND, data);
+    data = qpci_config_readw(ahci, PCI_COMMAND);
+#endif
+
+    /* These bits should now test as on. */
+    data = qpci_config_readw(ahci, PCI_COMMAND);
+    assert_bit_set(data, PCI_COMMAND_IO);
+    assert_bit_set(data, PCI_COMMAND_MEMORY);
+    assert_bit_set(data, PCI_COMMAND_MASTER);
+#ifdef USE_MSI
+    assert_bit_set(data, PCI_COMMAND_INTX_DISABLE);
+#endif
+
+    return ahci;
+}
+
 /*** Specification Adherence Tests ***/
 
 /**
@@ -440,6 +500,19 @@ static void test_pci_spec(void)
     ahci_shutdown(ahci);
 }
 
+/**
+ * Engage the PCI AHCI device and sanity check the response.
+ * Perform additional PCI config space bringup for the HBA.
+ */
+static void test_pci_enable(void)
+{
+    QPCIDevice *ahci;
+    HBA *hba_base;
+    ahci_boot(&ahci);
+    ahci_pci_enable(ahci, &hba_base);
+    ahci_shutdown(ahci);
+}
+
 
/******************************************************************************/
 
 int main(int argc, char **argv)
@@ -468,6 +541,7 @@ int main(int argc, char **argv)
     /* Run the tests */
     qtest_add_func("/ahci/sanity",     test_sanity);
     qtest_add_func("/ahci/pci_spec",   test_pci_spec);
+    qtest_add_func("/ahci/pci_enable", test_pci_enable);
 
     ret = g_test_run();
 
-- 
1.9.3