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[Qemu-devel] [PATCH 07/15] target-tricore: Add instructions of SRR opcod
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PATCH 07/15] target-tricore: Add instructions of SRR opcode format |
Date: |
Mon, 7 Jul 2014 19:13:34 +0100 |
Add instructions of SRR opcode format.
Add micro-op generator function for ssov.
Signed-off-by: Bastian Koppelmann <address@hidden>
---
target-tricore/translate.c | 140 ++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 139 insertions(+), 1 deletion(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index ad595b2..108619c 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -203,14 +203,34 @@ static void gen_shaci(TCGv ret, TCGv r1, int32_t con)
tcg_temp_free(temp);
}
+static inline void gen_ssov(TCGv ret, TCGv arg, int32_t cons)
+{
+ int l1 = gen_new_label();
+ TCGv temp = tcg_temp_local_new();
+ int32_t max_pos = (0x1u << (cons - 1)) - 1;
+ int32_t max_neg = -(0x1u << (cons - 1));
+
+ tcg_gen_movi_tl(temp, max_pos);
+ tcg_gen_brcondi_tl(TCG_COND_GT, arg, max_pos, l1);
+ tcg_gen_movi_tl(temp, max_neg);
+ tcg_gen_brcondi_tl(TCG_COND_LT, arg, max_neg, l1);
+ tcg_gen_mov_tl(temp, arg);
+ gen_set_label(l1);
+ tcg_gen_mov_tl(ret, temp);
+
+ tcg_temp_free(temp);
+}
+
/*
* Functions for decoding instructions
*/
static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
{
target_ulong op1;
- int r1;
+ int r1, r2;
uint16_t const16;
+ TCGv temp;
+
op1 = MASK_OP_MAJOR(ctx->opcode);
switch (op1) {
@@ -294,6 +314,124 @@ static void decode_16Bit_opc(CPUTRICOREState *env,
DisasContext *ctx)
/* FIXME: const too long */
gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const16 & 0x1f);
break;
+/* SRR-Format */
+ case OPC1_16_SRR_ADD:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ tcg_gen_add_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_ADD_A15:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ tcg_gen_add_tl(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_ADD_15A:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ tcg_gen_add_tl(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_ADD_A:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]);
+ break;
+ case OPC1_16_SRR_ADDS:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+
+ temp = tcg_temp_local_new();
+ tcg_gen_add_tl(temp, cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ gen_ssov(cpu_gpr_d[r1], temp, 32);
+ tcg_temp_free(temp);
+ break;
+ case OPC1_16_SRR_AND:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_CMOV:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ gen_cond_mov(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2],
+ cpu_gpr_d[r1], cpu_gpr_d[15]);
+ break;
+ case OPC1_16_SRR_CMOVN:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ gen_cond_mov(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
+ cpu_gpr_d[r1], cpu_gpr_d[15]);
+ break;
+ case OPC1_16_SRR_EQ:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+
+ tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
+ cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_LT:
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
+ cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_MOV:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_MOV_A:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_MOV_AA:
+ r1 = MASK_OP_SRR_S2(ctx->opcode);
+ r2 = MASK_OP_SRR_S1D(ctx->opcode);
+ tcg_gen_mov_tl(cpu_gpr_a[r2], cpu_gpr_a[r1]);
+ break;
+ case OPC1_16_SRR_MOV_D:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]);
+ break;
+ case OPC1_16_SRR_MUL:
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ tcg_gen_mul_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_OR:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_SUB:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ tcg_gen_sub_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_SUB_A15B:
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ tcg_gen_sub_tl(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_SUB_15AB:
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ tcg_gen_sub_tl(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
+ case OPC1_16_SRR_SUBS:
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ temp = tcg_temp_local_new();
+ tcg_gen_sub_tl(temp, cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ gen_ssov(cpu_gpr_d[r1], temp, 32);
+ tcg_temp_free(temp);
+ break;
+ case OPC1_16_SRR_XOR:
+ r1 = MASK_OP_SRR_S1D(ctx->opcode);
+ r2 = MASK_OP_SRR_S2(ctx->opcode);
+ tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ break;
}
}
--
2.0.1
- Re: [Qemu-devel] [PATCH 01/15] target-tricore: Add target stubs and qom-cpu, (continued)
- [Qemu-devel] [PATCH 08/15] target-tricore: Add instructions of SSR opcode format, Bastian Koppelmann, 2014/07/07
- [Qemu-devel] [PATCH 10/15] target-tricore: Add instructions of SB opcode format, Bastian Koppelmann, 2014/07/07
- [Qemu-devel] [PATCH 14/15] target-tricore: Add instructions of SLR, SSRO and SRO opcode format, Bastian Koppelmann, 2014/07/07
- [Qemu-devel] [PATCH 03/15] target-tricore: Add softmmu support, Bastian Koppelmann, 2014/07/07
- [Qemu-devel] [PATCH 09/15] target-tricore: Add instructions of SRRS and SLRO opcode format., Bastian Koppelmann, 2014/07/07
- [Qemu-devel] [PATCH 07/15] target-tricore: Add instructions of SRR opcode format,
Bastian Koppelmann <=
- [Qemu-devel] [PATCH 02/15] target-tricore: Add board for systemmode, Bastian Koppelmann, 2014/07/07