[Qemu-devel] [PATCH v3 08/11] target-arm: introduce tbflag for CPSR.E

[Paolo Bonzini]

Together with the existing tb flag for SCTLR.B, this governs the
endianness of data accesses.  Note that TARGET_WORDS_BIGENDIAN is
not used, the two flags are enough because linux-user/main.c
initializes SCTRL.B and CPSR.E correctly.

Similar to bswap_code, the new predicate arm_tbflag_is_data_be only
honors SCTLR.B in user-mode emulation.  For system-mode emulation,
SCTLR.B only affects the bottom two bits of the address and all accesses
are little endian.

Now that CPSR.E is handled at translation time, implementing setend will
be trivial.

Signed-off-by: Paolo Bonzini <address@hidden>
---
 target-arm/cpu.h       | 17 +++++++++++++++++
 target-arm/translate.c | 40 +++++++++++++++++++++++++---------------
 target-arm/translate.h |  2 ++
 3 files changed, 44 insertions(+), 15 deletions(-)

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index defd65e..a91fb4d 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1136,6 +1136,8 @@ static inline int cpu_mmu_index (CPUARMState *env)
 #define ARM_TBFLAG_SCTLR_B_MASK     (1 << ARM_TBFLAG_SCTLR_B_SHIFT)
 #define ARM_TBFLAG_CPACR_FPEN_SHIFT 17
 #define ARM_TBFLAG_CPACR_FPEN_MASK  (1 << ARM_TBFLAG_CPACR_FPEN_SHIFT)
+#define ARM_TBFLAG_CPSR_E_SHIFT     18
+#define ARM_TBFLAG_CPSR_E_MASK      (1 << ARM_TBFLAG_CPSR_E_SHIFT)
 
 /* Bit usage when in AArch64 state */
 #define ARM_TBFLAG_AA64_EL_SHIFT    0
@@ -1162,6 +1164,8 @@ static inline int cpu_mmu_index (CPUARMState *env)
     (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT)
 #define ARM_TBFLAG_CPACR_FPEN(F) \
     (((F) & ARM_TBFLAG_CPACR_FPEN_MASK) >> ARM_TBFLAG_CPACR_FPEN_SHIFT)
+#define ARM_TBFLAG_CPSR_E(F) \
+    (((F) & ARM_TBFLAG_CPSR_E_MASK) >> ARM_TBFLAG_CPSR_E_SHIFT)
 #define ARM_TBFLAG_AA64_EL(F) \
     (((F) & ARM_TBFLAG_AA64_EL_MASK) >> ARM_TBFLAG_AA64_EL_SHIFT)
 #define ARM_TBFLAG_AA64_FPEN(F) \
@@ -1192,6 +1196,7 @@ static inline bool bswap_code(bool sctlr_b)
 #endif
 }
 
+
 #ifdef CONFIG_USER_ONLY
 /* get_user and put_user respectivaly return and expect data according
  * to TARGET_WORDS_BIGENDIAN, but ldrex/strex emulation needs to take
@@ -1220,6 +1225,15 @@ static inline bool arm_cpu_bswap_data(CPUARMState *env)
 }
 #endif
 
+static inline bool arm_tbflag_is_data_be(unsigned tbflags)
+{
+    return
+#ifdef CONFIG_USER_ONLY
+        ARM_TBFLAG_SCTLR_B(tbflags) ^
+#endif
+        ARM_TBFLAG_CPSR_E(tbflags);
+}
+
 static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
                                         target_ulong *cs_base, int *flags)
 {
@@ -1255,6 +1269,9 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, 
target_ulong *pc,
         if (fpen == 3 || (fpen == 1 && arm_current_pl(env) != 0)) {
             *flags |= ARM_TBFLAG_CPACR_FPEN_MASK;
         }
+        if (env->uncached_cpsr & CPSR_E) {
+            *flags |= ARM_TBFLAG_CPSR_E_MASK;
+        }
     }
 
     *cs_base = 0;
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 4f36d48..8be8f21 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -840,23 +840,27 @@ static inline void store_reg_from_load(CPUARMState *env, 
DisasContext *s,
 #define DO_GEN_LD(SUFF, OPC)                                             \
 static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, TCGv_i32 
addr, int index) \
 {                                                                        \
-    tcg_gen_qemu_ld_i32(val, addr, index, OPC);                          \
+    TCGMemOp opc = (OPC) | s->mo_endianness;                             \
+    tcg_gen_qemu_ld_i32(val, addr, index, opc);                          \
 }
 
 #define DO_GEN_ST(SUFF, OPC)                                             \
 static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, TCGv_i32 
addr, int index) \
 {                                                                        \
-    tcg_gen_qemu_st_i32(val, addr, index, OPC);                          \
+    TCGMemOp opc = (OPC) | s->mo_endianness;                             \
+    tcg_gen_qemu_st_i32(val, addr, index, opc);                          \
 }
 
 static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val, TCGv_i32 addr, 
int index)
 {
-    tcg_gen_qemu_ld_i64(val, addr, index, MO_TEQ);
+    TCGMemOp opc = MO_Q | s->mo_endianness;
+    tcg_gen_qemu_ld_i64(val, addr, index, opc);
 }
 
 static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, TCGv_i32 addr, 
int index)
 {
-    tcg_gen_qemu_st_i64(val, addr, index, MO_TEQ);
+    TCGMemOp opc = MO_Q | s->mo_endianness;
+    tcg_gen_qemu_st_i64(val, addr, index, opc);
 }
 
 #else
@@ -864,34 +868,38 @@ static inline void gen_aa32_st64(DisasContext *s, 
TCGv_i64 val, TCGv_i32 addr, i
 #define DO_GEN_LD(SUFF, OPC)                                             \
 static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, TCGv_i32 
addr, int index) \
 {                                                                        \
+    TCGMemOp opc = (OPC) | s->mo_endianness;                             \
     TCGv addr64 = tcg_temp_new();                                        \
     tcg_gen_extu_i32_i64(addr64, addr);                                  \
-    tcg_gen_qemu_ld_i32(val, addr64, index, OPC);                        \
+    tcg_gen_qemu_ld_i32(val, addr64, index, opc);                        \
     tcg_temp_free(addr64);                                               \
 }
 
 #define DO_GEN_ST(SUFF, OPC)                                             \
 static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, TCGv_i32 
addr, int index) \
 {                                                                        \
+    TCGMemOp opc = (OPC) | s->mo_endianness;                             \
     TCGv addr64 = tcg_temp_new();                                        \
     tcg_gen_extu_i32_i64(addr64, addr);                                  \
-    tcg_gen_qemu_st_i32(val, addr64, index, OPC);                        \
+    tcg_gen_qemu_st_i32(val, addr64, index, opc);                        \
     tcg_temp_free(addr64);                                               \
 }
 
 static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val, TCGv_i32 addr, 
int index)
 {
+    TCGMemOp opc = MO_Q | s->mo_endianness;
     TCGv addr64 = tcg_temp_new();
     tcg_gen_extu_i32_i64(addr64, addr);
-    tcg_gen_qemu_ld_i64(val, addr64, index, MO_TEQ);
+    tcg_gen_qemu_ld_i64(val, addr64, index, opc);
     tcg_temp_free(addr64);
 }
 
 static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, TCGv_i32 addr, 
int index)
 {
+    TCGMemOp opc = MO_Q | s->mo_endianness;
     TCGv addr64 = tcg_temp_new();
     tcg_gen_extu_i32_i64(addr64, addr);
-    tcg_gen_qemu_st_i64(val, addr64, index, MO_TEQ);
+    tcg_gen_qemu_st_i64(val, addr64, index, opc);
     tcg_temp_free(addr64);
 }
 
@@ -899,12 +907,12 @@ static inline void gen_aa32_st64(DisasContext *s, 
TCGv_i64 val, TCGv_i32 addr, i
 
 DO_GEN_LD(8s, MO_SB)
 DO_GEN_LD(8u, MO_UB)
-DO_GEN_LD(16s, MO_TESW)
-DO_GEN_LD(16u, MO_TEUW)
-DO_GEN_LD(32u, MO_TEUL)
+DO_GEN_LD(16s, MO_SW)
+DO_GEN_LD(16u, MO_UW)
+DO_GEN_LD(32u, MO_UL)
 DO_GEN_ST(8, MO_UB)
-DO_GEN_ST(16, MO_TEUW)
-DO_GEN_ST(32, MO_TEUL)
+DO_GEN_ST(16, MO_UW)
+DO_GEN_ST(32, MO_UL)
 
 static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
 {
@@ -7552,7 +7560,7 @@ static void disas_arm_insn(CPUARMState * env, 
DisasContext *s)
         if ((insn & 0x0ffffdff) == 0x01010000) {
             ARCH(6);
             /* setend */
-            if (((insn >> 9) & 1) != bswap_code(s->sctlr_b)) {
+            if (((insn >> 9) & 1) != s->cpsr_e) {
                 /* Dynamic endianness switching not implemented. */
                 qemu_log_mask(LOG_UNIMP, "arm: unimplemented setend\n");
                 goto illegal_op;
@@ -10719,7 +10727,7 @@ static void disas_thumb_insn(CPUARMState *env, 
DisasContext *s)
             case 2:
                 /* setend */
                 ARCH(6);
-                if (((insn >> 3) & 1) != bswap_code(s->sctlr_b)) {
+                if (((insn >> 3) & 1) != s->cpsr_e) {
                     /* Dynamic endianness switching not implemented. */
                     qemu_log_mask(LOG_UNIMP, "arm: unimplemented setend\n");
                     goto illegal_op;
@@ -10900,6 +10908,8 @@ static inline void 
gen_intermediate_code_internal(ARMCPU *cpu,
     dc->aarch64 = 0;
     dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
     dc->sctlr_b = ARM_TBFLAG_SCTLR_B(tb->flags);
+    dc->cpsr_e = ARM_TBFLAG_CPSR_E(tb->flags);
+    dc->mo_endianness = arm_tbflag_is_data_be(tb->flags) ? MO_BE : MO_LE;
     dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;
     dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4;
 #if !defined(CONFIG_USER_ONLY)
diff --git a/target-arm/translate.h b/target-arm/translate.h
index 19f794c..928c1c3 100644
--- a/target-arm/translate.h
+++ b/target-arm/translate.h
@@ -17,6 +17,8 @@ typedef struct DisasContext {
     int singlestep_enabled;
     int thumb;
     int sctlr_b;
+    int cpsr_e;
+    TCGMemOp mo_endianness;
 #if !defined(CONFIG_USER_ONLY)
     int user;
 #endif
-- 
1.9.3