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[Qemu-devel] [PATCH v3 13/32] target-arm: implement IRQ/FIQ routing to M
From: |
Fabian Aggeler |
Subject: |
[Qemu-devel] [PATCH v3 13/32] target-arm: implement IRQ/FIQ routing to Monitor mode |
Date: |
Wed, 11 Jun 2014 01:54:55 +0200 |
SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU
mode. When taking IRQ exception to monitor mode FIQ exception is
additionally masked.
Signed-off-by: Sergey Fedorov <address@hidden>
Signed-off-by: Fabian Aggeler <address@hidden>
---
target-arm/helper.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index b9b458e..2fbecfa 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3705,12 +3705,21 @@ void arm_cpu_do_interrupt(CPUState *cs)
/* Disable IRQ and imprecise data aborts. */
mask = CPSR_A | CPSR_I;
offset = 4;
+ if (env->cp15.scr_el3 & SCR_IRQ) {
+ /* IRQ routed to monitor mode */
+ new_mode = ARM_CPU_MODE_MON;
+ mask |= CPSR_F;
+ }
break;
case EXCP_FIQ:
new_mode = ARM_CPU_MODE_FIQ;
addr = 0x1c;
/* Disable FIQ, IRQ and imprecise data aborts. */
mask = CPSR_A | CPSR_I | CPSR_F;
+ if (env->cp15.scr_el3 & SCR_FIQ) {
+ /* FIQ routed to monitor mode */
+ new_mode = ARM_CPU_MODE_MON;
+ }
offset = 4;
break;
case EXCP_SMC:
--
1.8.3.2
- Re: [Qemu-devel] [PATCH v3 15/32] target-arm: add NSACR register, (continued)
- [Qemu-devel] [PATCH v3 13/32] target-arm: implement IRQ/FIQ routing to Monitor mode,
Fabian Aggeler <=
- [Qemu-devel] [PATCH v3 09/32] target-arm: extend Aarch32 async excp masking, Fabian Aggeler, 2014/06/10
- [Qemu-devel] [PATCH v3 12/32] target-arm: use dedicated target_el function, Fabian Aggeler, 2014/06/10
- [Qemu-devel] [PATCH v3 11/32] target-arm: add async excp target_el&mode function, Fabian Aggeler, 2014/06/10
- [Qemu-devel] [PATCH v3 04/32] target-arm: add arm_is_secure() function, Fabian Aggeler, 2014/06/10