Re: [Qemu-devel] [PATCH v2] target-arm: implement PD0/PD1 bits for TTBCR

[Aggeler Fabian]

On 09 Jun 2014, at 17:18, Peter Maydell <address@hidden> wrote:

> On 9 June 2014 12:27, Peter Maydell <address@hidden> wrote:
>> On 5 June 2014 11:39, Fabian Aggeler <address@hidden> wrote:
>>> Corrected handling of writes to TTBCR for ARMv8 (previously UNK/SBZP
>>> bits are not RES0) and ARMv7 (new bits PD0/PD1 for CPUs with Security
>>> Extensions).
>>> 
>>> Bits PD0/PD1 are now respected in get_phys_addr_v6/v5() and
>>> get_level1_table_address.
>>> 
>>> Signed-off-by: Fabian Aggeler <address@hidden>
>> 
>> Applied to target-arm.next.
> 
> Unapplied -- the 'goto do_fault' codepaths in get_phys_addr_v5()
> end up using 'domain' in constructing the returned fault status
> code without ever initialising it.
> 
> Since this is a first level Translation fault, the DFSR Domain
> field is UNKNOWN, so it should be sufficient to set it to 0.
> You might as well just set it to 0 when it's defined at the top
> of the function, as get_phys_addr_v6() does.
> 
> thanks
> -- PMM

Thanks, I will send a v3 with domain initialised.

Fabian