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[Qemu-devel] [PULL 10/20] target-arm: arm_any_initfn() should never set
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 10/20] target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64 |
Date: |
Mon, 9 Jun 2014 15:57:28 +0100 |
The arm_any_initfn() is used only for the 32-bit linux-user "cpu any",
so it only gets called in builds where TARGET_AARCH64 is not defined.
Remove the unreachable line which sets ARM_FEATURE_AARCH64.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
---
target-arm/cpu.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index fb9c12d..94123b2 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -963,9 +963,6 @@ static void arm_any_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
set_feature(&cpu->env, ARM_FEATURE_V7MP);
set_feature(&cpu->env, ARM_FEATURE_CRC);
-#ifdef TARGET_AARCH64
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
-#endif
cpu->midr = 0xffffffff;
}
#endif
--
1.9.2
- [Qemu-devel] [PULL 00/20] target-arm queue, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 20/20] target-arm: Delete unused iwmmxt_msadb helper, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 18/20] target-arm: A64: Implement two-register SHA instructions, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 19/20] target-arm: Fix errors in writes to generic timer control registers, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 15/20] target-arm: A32/T32: Mask CRC value in calling code, not helper, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 16/20] target-arm: A64: Implement AES instructions, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 13/20] target-arm: VFPv4 implies half-precision extension, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 14/20] target-arm: A64: Implement CRC instructions, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 11/20] target-arm: Remove unnecessary setting of feature bits, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 09/20] target-arm: A64: Use PMULL feature bit for PMULL, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 10/20] target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64,
Peter Maydell <=
- [Qemu-devel] [PULL 07/20] target-arm: Allow 3reg_wide undefreq to encode more bad size options, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 08/20] target-arm: add support for v8 VMULL.P64 instruction, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 17/20] target-arm: A64: Implement 3-register SHA instructions, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 05/20] target-arm: Correct handling of UXN bit in ARMv8 LPAE page tables, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 12/20] target-arm: Clean up handling of ARMv8 optional feature bits, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 02/20] target-arm/cpu64.c: Actually register Cortex-A57 impdef registers, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 04/20] target-arm: implement PD0/PD1 bits for TTBCR, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 01/20] vexpress: Add support for the -bios flag to provide firmware, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 06/20] target-arm: add support for v8 SHA1 and SHA256 instructions, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 03/20] target-arm: Prepare cpreg writefns/readfns for EL3/SecExt, Peter Maydell, 2014/06/09