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Re: [Qemu-devel] [PATCH v5 00/30] book3s powerpc classes (970, power5, p


From: Alexey Kardashevskiy
Subject: Re: [Qemu-devel] [PATCH v5 00/30] book3s powerpc classes (970, power5, power7, power8) rework
Date: Thu, 05 Jun 2014 09:37:20 +1000
User-agent: Mozilla/5.0 (X11; Linux i686 on x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0

On 06/05/2014 07:51 AM, Alexander Graf wrote:
> 
> On 04.06.14 19:37, Tom Musta wrote:
>> On 6/4/2014 7:50 AM, Alexey Kardashevskiy wrote:
>>> Started as POWER7/8 SPRs patchset, this became a rework of book3s/970 CPU
>>> classes initialization.
>>>
>>> The aim is to boot little endian guests in TCG mode with -cpu POWER8
>>> (ironically, POWER8 emulation still fails, debugging it now but most of
>>> the set
>>> is still valid).
>>>
>>> Individual patches have change logs.
>>>
>>> Compared to v4, this has one more patch - "target-ppc: Make UCTRL a
>>> mirror of CTRL"
>>>
>>> Please comment. I could have forgotten some RB's... Thanks!
>>>
>>>
>>> Alexey Kardashevskiy (30):
>>>    target-ppc: Rename 7XX/60x/74XX/e600 PMU SPRs
>>>    target-ppc: Merge 970FX and 970MP into a single 970 class
>>>    target-ppc: Refactor PPC970
>>>    target-ppc: Make UCTRL a mirror of CTRL
>>>    target-ppc: Copy and split gen_spr_7xx() for 970
>>>    target-ppc: Add "POWER" prefix to MMCRA PMU registers
>>>    target-ppc: Add PMC5/6, SDAR and MMCRA to 970 family
>>>    target-ppc: Add PMC7/8 to 970 class
>>>    target-ppc: Add HID4 SPR for PPC970
>>>    target-ppc: Introduce and reuse generalized init_proc_book3s_64()
>>>    target-ppc: Remove check_pow_970FX
>>>    target-ppc: Enable PMU SPRs migration
>>>    target-ppc: Move POWER7/8 PIR/PURR/SPURR SPR registration to helpers
>>>    target-ppc: Move POWER8 TCE Address control (TAR) to a helper
>>>    target-ppc: Move POWER7/8 CFAR/DSCR/CTRL/PPR/PCR SPR registration to
>>>      helpers
>>>    target-ppc: Make use of gen_spr_book3s_altivec() for POWER7/8
>>>    target-ppc: Make use of gen_spr_power5p_lpar() for POWER7/8
>>>    target-ppc: Switch POWER7/8 classes to use correct PMU SPRs
>>>    target-ppc: Refactor class init for POWER7/8
>>>    target-ppc: Add POWER8's TIR SPR
>>>    target-ppc: Add POWER8's FSCR SPR
>>>    target-ppc: Enable FSCR facility check for TAR
>>>    target-ppc: Add POWER8's MMCR2/MMCRS SPRs
>>>    target-ppc: Add POWER8's TM SPRs
>>>    KVM: target-ppc: Enable TM state migration
>>>    target-ppc: Add POWER8's Event Based Branch (EBB) control SPRs
>>>    target-ppc: Enable PPR and VRSAVE SPRs migration
>>>    target-ppc: Enable DABRX SPR and limit it to <=POWER7
>>>    spapr_hcall: Split h_set_mode()
>>>    spapr_hcall: Add address-translation-mode-on-interrupt resource in
>>>      H_SET_MODE
>>>
>>>   hw/ppc/spapr_hcall.c        |  114 +++--
>>>   include/hw/ppc/spapr.h      |    5 +
>>>   target-ppc/cpu-models.c     |   14 +-
>>>   target-ppc/cpu.h            |  128 +++++-
>>>   target-ppc/excp_helper.c    |   12 +-
>>>   target-ppc/helper.h         |    2 +
>>>   target-ppc/kvm.c            |   38 ++
>>>   target-ppc/machine.c        |   35 ++
>>>   target-ppc/misc_helper.c    |   39 ++
>>>   target-ppc/translate.c      |    7 +
>>>   target-ppc/translate_init.c | 1072
>>> ++++++++++++++++++++++++++-----------------
>>>   11 files changed, 977 insertions(+), 489 deletions(-)
>>>
>> Alexey/Alex:
>>
>> I think this looks good.  And I was able to boot an Ubuntu 14.04 image
>> using Power8 TCG:
> 
> Nice :).
> 
> Thanks, applied to ppc-next.


Heh. This missed pull request :)



-- 
Alexey



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