Re: [Qemu-devel] [PATCH 01/21] target-mips: introduce MIPS64R6 ISA and a new generic CPU

[Aurelien Jarno]

On Fri, May 30, 2014 at 03:47:39PM +0100, Leon Alrae wrote:
> Define ISA_MIPS64R6 and add MIPS64R6-generic core supporting new ISA.
> Additionally define ISA_MIPS64R3 and ISA_MIPS64R5 to fill the gap.
> 
> Signed-off-by: Leon Alrae <address@hidden>
> ---
>  target-mips/mips-defs.h      |   28 +++++++++++++++++++---------
>  target-mips/translate_init.c |   29 +++++++++++++++++++++++++++++
>  2 files changed, 48 insertions(+), 9 deletions(-)
> 
> diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
> index 9dfa516..6cb62b2 100644
> --- a/target-mips/mips-defs.h
> +++ b/target-mips/mips-defs.h
> @@ -30,17 +30,21 @@
>  #define              ISA_MIPS64      0x00000080
>  #define              ISA_MIPS64R2    0x00000100
>  #define   ISA_MIPS32R3  0x00000200
> -#define   ISA_MIPS32R5  0x00000400
> +#define   ISA_MIPS64R3  0x00000400
> +#define   ISA_MIPS32R5  0x00000800
> +#define   ISA_MIPS64R5  0x00001000
> +#define   ISA_MIPS32R6  0x00002000
> +#define   ISA_MIPS64R6  0x00004000
>  
>  /* MIPS ASEs. */
> -#define              ASE_MIPS16      0x00001000
> -#define              ASE_MIPS3D      0x00002000
> -#define              ASE_MDMX        0x00004000
> -#define              ASE_DSP         0x00008000
> -#define              ASE_DSPR2       0x00010000
> -#define              ASE_MT          0x00020000
> -#define              ASE_SMARTMIPS   0x00040000
> -#define      ASE_MICROMIPS   0x00080000
> +#define   ASE_MIPS16    0x00010000
> +#define   ASE_MIPS3D    0x00020000
> +#define   ASE_MDMX      0x00040000
> +#define   ASE_DSP       0x00080000
> +#define   ASE_DSPR2     0x00100000
> +#define   ASE_MT        0x00200000
> +#define   ASE_SMARTMIPS 0x00400000
> +#define   ASE_MICROMIPS 0x00800000
>  
>  /* Chip specific instructions. */
>  #define              INSN_LOONGSON2E  0x20000000
> @@ -68,9 +72,15 @@
>  
>  /* MIPS Technologies "Release 3" */
>  #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
> +#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3)
>  
>  /* MIPS Technologies "Release 5" */
>  #define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
> +#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5)
> +
> +/* MIPS Technologies "Release 6" */
> +#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
> +#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6)
>  
>  /* Strictly follow the architecture standard:
>     - Disallow "special" instruction handling for PMON/SPIM.

This part looks fine.

> diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
> index 29dc2ef..0adbb19 100644
> --- a/target-mips/translate_init.c
> +++ b/target-mips/translate_init.c
> @@ -516,6 +516,35 @@ static const mips_def_t mips_defs[] =
>          .mmu_type = MMU_TYPE_R4000,
>      },
>      {
> +        /* A generic CPU providing MIPS64 Release 6 features.
> +           FIXME: Eventually this should be replaced by a real CPU model. */
> +        .name = "MIPS64R6-generic",
> +        .CP0_PRid = 0x00010000,
> +        .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
> +                       (MMU_TYPE_R4000 << CP0C0_MT),
> +        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
> +                       (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
> +                       (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
> +                       (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),

Do we really suppport watch registers or EJTAG in QEMU?

> +        .CP0_Config2 = MIPS_CONFIG2,
> +        .CP0_Config3 = MIPS_CONFIG3,
> +        .CP0_LLAddr_rw_bitmask = 0,
> +        .CP0_LLAddr_shift = 0,
> +        .SYNCI_Step = 32,
> +        .CCRes = 2,
> +        .CP0_Status_rw_bitmask = 0x30D8FFFF,
> +        .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
> +                    (1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) |
> +                    (0x0 << FCR0_REV),
> +        .SEGBITS = 42,
> +        /* The architectural limit is 59, but we have hardcoded 36 bit
> +           in some places...
> +        .PABITS = 59, */ /* the architectural limit */
> +        .PABITS = 36,
> +        .insn_flags = CPU_MIPS64R6,
> +        .mmu_type = MMU_TYPE_R4000,
> +    },

This part should be moved to a patch that is last in the series, so that
such a CPU is selectable only when it is fully implemented.


-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
address@hidden                 http://www.aurel32.net