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[Qemu-devel] [PULL 15/26] target-arm: A64: Introduce aarch64_banked_spsr
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 15/26] target-arm: A64: Introduce aarch64_banked_spsr_index() |
Date: |
Tue, 27 May 2014 17:28:23 +0100 |
From: "Edgar E. Iglesias" <address@hidden>
Add aarch64_banked_spsr_index(), used to map an Exception Level
to an index in the banked_spsr array.
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper-a64.c | 2 +-
target-arm/internals.h | 14 ++++++++++++++
target-arm/op_helper.c | 3 ++-
3 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index b8e6d56..b970fd1 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -488,7 +488,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
}
if (is_a64(env)) {
- env->banked_spsr[0] = pstate_read(env);
+ env->banked_spsr[aarch64_banked_spsr_index(1)] = pstate_read(env);
env->sp_el[arm_current_pl(env)] = env->xregs[31];
env->xregs[31] = env->sp_el[1];
env->elr_el[1] = env->pc;
diff --git a/target-arm/internals.h b/target-arm/internals.h
index d63a975..c9897c2 100644
--- a/target-arm/internals.h
+++ b/target-arm/internals.h
@@ -75,6 +75,20 @@ static inline void arm_log_exception(int idx)
*/
#define GTIMER_SCALE 16
+/*
+ * For AArch64, map a given EL to an index in the banked_spsr array.
+ */
+static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
+{
+ static const unsigned int map[4] = {
+ [1] = 0, /* EL1. */
+ [2] = 6, /* EL2. */
+ [3] = 7, /* EL3. */
+ };
+ assert(el >= 1 && el <= 3);
+ return map[el];
+}
+
int bank_number(int mode);
void switch_mode(CPUARMState *, int);
void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index f120b02..c2b4bf0 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -386,7 +386,8 @@ void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op,
uint32_t imm)
void HELPER(exception_return)(CPUARMState *env)
{
- uint32_t spsr = env->banked_spsr[0];
+ unsigned int spsr_idx = aarch64_banked_spsr_index(1);
+ uint32_t spsr = env->banked_spsr[spsr_idx];
int new_el, i;
if (env->pstate & PSTATE_SP) {
--
1.9.2
- [Qemu-devel] [PULL 11/26] target-arm: c12_vbar -> vbar_el[], (continued)
- [Qemu-devel] [PULL 11/26] target-arm: c12_vbar -> vbar_el[], Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 26/26] target-arm: A64: Register VBAR_EL3, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 10/26] target-arm: Make esr_el1 an array, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 24/26] target-arm: Make vbar_write writeback to any CPREG, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 22/26] target-arm: A64: Generalize ERET to various ELs, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 21/26] target-arm: A64: Trap ERET from EL0 at translation time, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 17/26] target-arm: Add a feature flag for EL3, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 18/26] target-arm: Register EL2 versions of ELR and SPSR, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 19/26] target-arm: Register EL3 versions of ELR and SPSR, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 16/26] target-arm: Add a feature flag for EL2, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 15/26] target-arm: A64: Introduce aarch64_banked_spsr_index(),
Peter Maydell <=
- [Qemu-devel] [PULL 23/26] target-arm: A64: Generalize update_spsel for the various ELs, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 25/26] target-arm: A64: Register VBAR_EL2, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 14/26] target-arm: Add SPSR entries for EL2/HYP and EL3/MON, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 08/26] target-arm: Use a 1:1 mapping between EL and MMU index, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 13/26] target-arm: A64: Add ELR entries for EL2 and 3, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 20/26] target-arm: A64: Forbid ERET to higher or unimplemented ELs, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 05/26] target-arm/translate.c: Clean up mmu index handling for ldrt/strt, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 06/26] target-arm/translate.c: Use get_mem_index() for SRS memory accesses, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 02/26] hw/display/pxa2xx_lcd: Fix 16bpp+alpha and 18bpp+alpha palette formats, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 07/26] target-arm: A32: Use get_mem_index for load/stores, Peter Maydell, 2014/05/27