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[Qemu-devel] [PATCH v5 15/23] target-arm: Register EL2 versions of ELR a
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v5 15/23] target-arm: Register EL2 versions of ELR and SPSR |
Date: |
Sun, 25 May 2014 11:08:44 +1000 |
From: "Edgar E. Iglesias" <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target-arm/helper.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 5e2eac3..81de010 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2077,6 +2077,19 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
REGINFO_SENTINEL
};
+static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
+ { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
+ .type = ARM_CP_NO_MIGRATE,
+ .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
+ .access = PL2_RW,
+ .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
+ { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
+ .type = ARM_CP_NO_MIGRATE,
+ .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
+ .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) },
+ REGINFO_SENTINEL
+};
+
static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -2328,6 +2341,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_arm_cp_regs(cpu, v8_cp_reginfo);
define_aarch64_debug_regs(cpu);
}
+ if (arm_feature(env, ARM_FEATURE_EL2)) {
+ define_arm_cp_regs(cpu, v8_el2_cp_reginfo);
+ }
if (arm_feature(env, ARM_FEATURE_MPU)) {
/* These are the MPU registers prior to PMSAv6. Any new
* PMSA core later than the ARM946 will require that we
--
1.8.3.2
- [Qemu-devel] [PATCH v5 05/23] target-arm: Use a 1:1 mapping between EL and MMU index, (continued)
- [Qemu-devel] [PATCH v5 05/23] target-arm: Use a 1:1 mapping between EL and MMU index, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 06/23] target-arm: Make elr_el1 an array, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 07/23] target-arm: Make esr_el1 an array, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 08/23] target-arm: c12_vbar -> vbar_el[], Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 09/23] target-arm: A64: Add SP entries for EL2 and 3, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 10/23] target-arm: A64: Add ELR entries for EL2 and 3, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 11/23] target-arm: Add SPSR entries for EL2/HYP and EL3/MON, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 12/23] target-arm: A64: Introduce aarch64_banked_spsr_index(), Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 13/23] target-arm: Add a feature flag for EL2, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 14/23] target-arm: Add a feature flag for EL3, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 15/23] target-arm: Register EL2 versions of ELR and SPSR,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v5 16/23] target-arm: Register EL3 versions of ELR and SPSR, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 17/23] target-arm: A64: Forbid ERET to higher or unimplemented ELs, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 18/23] target-arm: A64: Trap ERET from EL0 at translation time, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 19/23] target-arm: A64: Generalize ERET to various ELs, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 20/23] target-arm: A64: Generalize update_spsel for the various ELs, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 21/23] target-arm: Make vbar_write writeback to any CPREG, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 22/23] target-arm: A64: Register VBAR_EL2, Edgar E. Iglesias, 2014/05/24
- [Qemu-devel] [PATCH v5 23/23] target-arm: A64: Register VBAR_EL3, Edgar E. Iglesias, 2014/05/24