[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH 5/7] target-arm: add emulation of PSCI calls for
From: |
Rob Herring |
Subject: |
Re: [Qemu-devel] [PATCH 5/7] target-arm: add emulation of PSCI calls for system emulation |
Date: |
Wed, 14 May 2014 19:08:07 -0500 |
On Wed, May 14, 2014 at 1:12 PM, Peter Maydell <address@hidden> wrote:
> On 5 May 2014 17:00, Rob Herring <address@hidden> wrote:
>> From: Rob Herring <address@hidden>
>>
>> Add support for handling PSCI calls in system emulation. Both version
>> 0.1 and 0.2 of the PSCI spec are supported. Platforms can enable support
>> by setting "psci-method" QOM property on the cpus to SMC or HVC
>> emulation and having PSCI binding in their dtb.
[...]
>> + /* Initialize the cpu we are turning on */
>> + cpu_reset(cs);
>> + arm_cpu_set_pc(cs, entry);
>> + cpu->powered_off = false;
>> + cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
>> +
>> + /* Set the context_id in r0/x0 */
>> + if (is_a64(env)) {
>> + cpu->env.xregs[0] = context_id;
>> + } else {
>> + cpu->env.regs[0] = context_id;
>> + }
>
> If the calling CPU is in AArch32 then we're going
> to restart the target CPU in AArch64 but with R0
> set rather than X0. That doesn't seem right...
Probably just one on many issues to support A32 EL1... Since the core
is being reset and register state is undefined, I can just do:
cpu->env.xregs[0] = cpu->env.regs[0] = context_id;
EL2/3 support will then further complicate things (or just remove all
this code).
>> +
>> + ret = 0;
>> + break;
>> + case QEMU_PSCI_FN_CPU_OFF:
>> + case PSCI_0_2_FN_CPU_OFF:
>> + cpu->powered_off = true;
>> + cs->exit_request = 1;
>
> I need to check up on whether setting exit_request here
> is right, but I don't have time just this instant. More
> later :-)
IIRC, things did not work without it.
Rob
[Qemu-devel] [PATCH 4/7] target-arm: support AArch64 for arm_cpu_set_pc, Rob Herring, 2014/05/05