[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v2 04/23] target-arm: preserve RAO/WI bits of ARMv7
From: |
Fabian Aggeler |
Subject: |
[Qemu-devel] [PATCH v2 04/23] target-arm: preserve RAO/WI bits of ARMv7 SCTLR |
Date: |
Tue, 13 May 2014 18:15:49 +0200 |
From: Svetlana Fedoseeva <address@hidden>
Signed-off-by: Svetlana Fedoseeva <address@hidden>
Signed-off-by: Sergey Fedorov <address@hidden>
Signed-off-by: Fabian Aggeler <address@hidden>
---
target-arm/helper.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 9c3269f..2b57ad9 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2083,6 +2083,11 @@ static void sctlr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
{
ARMCPU *cpu = arm_env_get_cpu(env);
+ if (arm_feature(env, ARM_FEATURE_V7)) {
+ value |= SCTLR_XP | SCTLR_U | SCTLR_nTWE | SCTLR_nTWI | SCTLR_L
+ | SCTLR_CP15BEN | SCTLR_P; /* These bits are RAO/WI */
+ }
+
env->cp15.c1_sys = value;
/* ??? Lots of these bits are not implemented. */
/* This may enable/disable the MMU, so do a TLB flush. */
--
1.8.3.2
- Re: [Qemu-devel] [PATCH v2 10/23] target-arm: implement CPACR register logic, (continued)
Re: [Qemu-devel] [PATCH v2 10/23] target-arm: implement CPACR register logic, Peter Crosthwaite, 2014/05/14
[Qemu-devel] [PATCH v2 03/23] target-arm: adjust TTBCR for Security Extension feature, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 12/23] target-arm: add SDER definition, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 07/23] target-arm: reject switching to monitor mode from non-secure state, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 08/23] target-arm: adjust arm_current_pl() for Security Extensions, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 05/23] target-arm: add CPU Monitor mode, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 04/23] target-arm: preserve RAO/WI bits of ARMv7 SCTLR,
Fabian Aggeler <=
[Qemu-devel] [PATCH v2 22/23] target-arm: implement IRQ/FIQ routing to Monitor mode, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 11/23] target-arm: add NSACR support, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 14/23] target-arm: add banked coprocessor register type and macros, Fabian Aggeler, 2014/05/13