[Qemu-devel] [PATCH v2 20/23] target-arm: add MVBAR support

[Fabian Aggeler]

Use MVBAR register as exception vector base address for
exceptions taken to CPU monitor mode.

Signed-off-by: Sergey Fedorov <address@hidden>
Signed-off-by: Fabian Aggeler <address@hidden>
---
 target-arm/cpu.h    |  1 +
 target-arm/helper.c | 12 +++++++-----
 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 7893004..9b6f8bd 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -226,6 +226,7 @@ typedef struct CPUARMState {
         A32_BANKED_REG(uint64_t, tpidr_el0); /* User RW Thread register.  */
         A32_BANKED_REG(uint64_t, tpidrro_el0); /* User RO Thread register.  */
         A32_BANKED_REG(uint64_t, tpidr_el1); /* Privileged Thread register.  */
+        uint64_t c12_mvbar; /* (monitor) vector base address register */
         uint64_t c14_cntfrq; /* Counter Frequency register */
         uint64_t c14_cntkctl; /* Timer Control register */
         ARMGenericTimer c14_timer[NUM_GTIMERS];
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 618fd31..808b822 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2225,6 +2225,9 @@ static const ARMCPRegInfo tz_cp_reginfo[] = {
       .opc0 = 3, .crn = 6, .crm = 1, .opc1 = 0, .opc2 = 0,
       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
       .resetvalue = 0 },
+    { .name = "MVBAR", .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 1,
+      .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0,
+      .fieldoffset = offsetof(CPUARMState, cp15.c12_mvbar) },
     { .name = "SDER", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 1,
       .access = PL3_RW, .resetvalue = 0,
       .fieldoffset = offsetof(CPUARMState, cp15.c1_sder) },
@@ -3606,16 +3609,15 @@ void arm_cpu_do_interrupt(CPUState *cs)
         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
         return; /* Never happens.  Keep compiler happy.  */
     }
-    /* High vectors.  */
-    if (arm_current_sctlr(env) & SCTLR_V) {
+    if (new_mode == ARM_CPU_MODE_MON) {
+        addr += env->cp15.c12_mvbar;
+    } else if (arm_current_sctlr(env) & SCTLR_V) { /* High vectors.  */
         /* when enabled, base address cannot be remapped.  */
         addr += 0xffff0000;
     } else {
         /* ARM v7 architectures provide a vector base address register to remap
          * the interrupt vector table.
-         * This register is only followed in non-monitor mode, and has a secure
-         * and un-secure copy. Since the cpu is always in a un-secure operation
-         * and is never in monitor mode this feature is always active.
+         * This register is only followed in non-monitor mode, and is banked.
          * Note: only bits 31:5 are valid.
          */
         addr += A32_MAPPED_EL3_CURRENT_REG_GET(env, c12_vbar);
-- 
1.8.3.2