Re: [Qemu-devel] [PATCH v3 07/16] tcg-ppc64: DefineTCG_TARGET_INSN_UNIT_SIZEE

[Alex Bennée]

Richard Henderson <address@hidden> writes:

> On 04/29/2014 04:25 AM, Alex Bennée wrote:
>>> +static void reloc_pc24(tcg_insn_unit *pc, tcg_insn_unit *target)
>>>  {
>>> -    *(uint32_t *)pc = (*(uint32_t *)pc & ~0x3fffffc)
>>> -        | reloc_pc24_val(pc, target);
>>> +    *pc = (*pc & ~0x3fffffc) | reloc_pc24_val(pc, target);
>>>  }
>> 
>> Should 0x3fffffc be a #define'd mask? Can the PC ever actually be
>> non-word aligned?
>
> No, it can't be unaligned.  The 0x3fffffc is really the field into
> which the offset is being placed.  I don't think a define is helpful
> really, since this is the only place it's used.

Ahh ok that makes sense. I was thrown because the masking pattern seems
to occur all around the ppc tcg code:

16:40 address@hidden/x86_64 [qemu.git] >git grep "0x3fffffc"
disas/ppc.c:  { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | 
PPC_OPERAND_SIGNED },
disas/ppc.c:  { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | 
PPC_OPERAND_SIGNED },
tcg/ppc/tcg-target.c:    return disp & 0x3fffffc;
tcg/ppc/tcg-target.c:    *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
tcg/ppc/tcg-target.c:        tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
tcg/ppc/tcg-target.c:                tcg_out32 (s, B | (val & 0x3fffffc));
tcg/ppc64/tcg-target.c:    return disp & 0x3fffffc;
tcg/ppc64/tcg-target.c:    *(uint32_t *)pc = (*(uint32_t *)pc & ~0x3fffffc)
tcg/ppc64/tcg-target.c:    unsigned retrans = *(uint32_t *)s->code_ptr & 
0x3fffffc;
tcg/ppc64/tcg-target.c:        tcg_out32(s, B | (disp & 0x3fffffc) | mask);


>
>
> r~

-- 
Alex Bennée