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[Qemu-devel] [PULL 24/51] target-arm: Implement AArch64 view of ACTLR
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 24/51] target-arm: Implement AArch64 view of ACTLR |
Date: |
Thu, 17 Apr 2014 11:33:39 +0100 |
Implement the AArch64 view of the ACTLR (auxiliary control
register). Note that QEMU internally tends to call this
AUXCR for historical reasons.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
---
target-arm/helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 10300aa..32af1df 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2316,7 +2316,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
if (arm_feature(env, ARM_FEATURE_AUXCR)) {
ARMCPRegInfo auxcr = {
- .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 =
1,
+ .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
.access = PL1_RW, .type = ARM_CP_CONST,
.resetvalue = cpu->reset_auxcr
};
--
1.9.1
- [Qemu-devel] [PULL 33/51] target-arm: Implement CBAR for Cortex-A57, (continued)
- [Qemu-devel] [PULL 33/51] target-arm: Implement CBAR for Cortex-A57, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 35/51] target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 32/51] target-arm: Implement Cortex-A57 implementation-defined system registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 31/51] target-arm: Implement RVBAR register, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 29/51] target-arm: Implement auxiliary fault status registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 30/51] target-arm: Implement AArch64 address translation operations, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 40/51] allwinner-a10-pic: fix behaviour of pending register, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 27/51] target-arm: Don't expose wildcard ID register definitions for ARMv8, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 28/51] target-arm: Replace wildcarded cpreg definitions with precise ones for ARMv8, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 26/51] target-arm: Remove THUMB2EE feature from AArch64 'any' CPU, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 24/51] target-arm: Implement AArch64 view of ACTLR,
Peter Maydell <=
- [Qemu-devel] [PULL 20/51] target-arm: Implement ARMv8 MVFR registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 25/51] target-arm: Implement ISR_EL1 register, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 18/51] target-arm: Move arm_log_exception() into internals.h, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 21/51] target-arm: Add Cortex-A57 processor, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 19/51] target-arm: Implement AArch64 EL1 exception handling, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 22/51] target-arm: Implement AArch64 views of AArch32 ID registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 17/51] target-arm: Implement AArch64 SPSR_EL1, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 15/51] target-arm: Add AArch64 ELR_EL1 register., Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 16/51] target-arm: Implement SP_EL0, SP_EL1, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 23/51] target-arm: Implement AArch64 view of CONTEXTIDR, Peter Maydell, 2014/04/17