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[Qemu-devel] [PULL for-2.1 20/25] tcg-aarch64: Support stores of zero
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL for-2.1 20/25] tcg-aarch64: Support stores of zero |
Date: |
Wed, 16 Apr 2014 09:18:03 -0700 |
Reviewed-by: Claudio Fontana <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/aarch64/tcg-target.c | 35 +++++++++++++++++++----------------
1 file changed, 19 insertions(+), 16 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 34e477d..caaf8a2 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -1253,21 +1253,21 @@ static void tcg_out_qemu_st_direct(TCGContext *s,
TCGMemOp memop,
tcg_out_ldst_r(s, LDST_8, LDST_ST, data_r, addr_r, off_r);
break;
case MO_16:
- if (bswap) {
+ if (bswap && data_r != TCG_REG_XZR) {
tcg_out_rev16(s, TCG_TYPE_I32, TCG_REG_TMP, data_r);
data_r = TCG_REG_TMP;
}
tcg_out_ldst_r(s, LDST_16, LDST_ST, data_r, addr_r, off_r);
break;
case MO_32:
- if (bswap) {
+ if (bswap && data_r != TCG_REG_XZR) {
tcg_out_rev(s, TCG_TYPE_I32, TCG_REG_TMP, data_r);
data_r = TCG_REG_TMP;
}
tcg_out_ldst_r(s, LDST_32, LDST_ST, data_r, addr_r, off_r);
break;
case MO_64:
- if (bswap) {
+ if (bswap && data_r != TCG_REG_XZR) {
tcg_out_rev(s, TCG_TYPE_I64, TCG_REG_TMP, data_r);
data_r = TCG_REG_TMP;
}
@@ -1364,8 +1364,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_ld_i32:
case INDEX_op_ld_i64:
- case INDEX_op_st_i32:
- case INDEX_op_st_i64:
case INDEX_op_ld8u_i32:
case INDEX_op_ld8s_i32:
case INDEX_op_ld16u_i32:
@@ -1376,13 +1374,18 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_ld16s_i64:
case INDEX_op_ld32u_i64:
case INDEX_op_ld32s_i64:
+ tcg_out_ldst(s, aarch64_ldst_get_data(opc), aarch64_ldst_get_type(opc),
+ a0, a1, a2);
+ break;
+ case INDEX_op_st_i32:
+ case INDEX_op_st_i64:
case INDEX_op_st8_i32:
case INDEX_op_st8_i64:
case INDEX_op_st16_i32:
case INDEX_op_st16_i64:
case INDEX_op_st32_i64:
tcg_out_ldst(s, aarch64_ldst_get_data(opc), aarch64_ldst_get_type(opc),
- a0, a1, a2);
+ REG0(0), a1, a2);
break;
case INDEX_op_add_i32:
@@ -1585,7 +1588,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_qemu_st_i32:
case INDEX_op_qemu_st_i64:
- tcg_out_qemu_st(s, a0, a1, a2, args[3]);
+ tcg_out_qemu_st(s, REG0(0), a1, a2, args[3]);
break;
case INDEX_op_bswap32_i64:
@@ -1693,13 +1696,13 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_ld32s_i64, { "r", "r" } },
{ INDEX_op_ld_i64, { "r", "r" } },
- { INDEX_op_st8_i32, { "r", "r" } },
- { INDEX_op_st16_i32, { "r", "r" } },
- { INDEX_op_st_i32, { "r", "r" } },
- { INDEX_op_st8_i64, { "r", "r" } },
- { INDEX_op_st16_i64, { "r", "r" } },
- { INDEX_op_st32_i64, { "r", "r" } },
- { INDEX_op_st_i64, { "r", "r" } },
+ { INDEX_op_st8_i32, { "rZ", "r" } },
+ { INDEX_op_st16_i32, { "rZ", "r" } },
+ { INDEX_op_st_i32, { "rZ", "r" } },
+ { INDEX_op_st8_i64, { "rZ", "r" } },
+ { INDEX_op_st16_i64, { "rZ", "r" } },
+ { INDEX_op_st32_i64, { "rZ", "r" } },
+ { INDEX_op_st_i64, { "rZ", "r" } },
{ INDEX_op_add_i32, { "r", "r", "rwA" } },
{ INDEX_op_add_i64, { "r", "r", "rA" } },
@@ -1753,8 +1756,8 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_qemu_ld_i32, { "r", "l" } },
{ INDEX_op_qemu_ld_i64, { "r", "l" } },
- { INDEX_op_qemu_st_i32, { "l", "l" } },
- { INDEX_op_qemu_st_i64, { "l", "l" } },
+ { INDEX_op_qemu_st_i32, { "lZ", "l" } },
+ { INDEX_op_qemu_st_i64, { "lZ", "l" } },
{ INDEX_op_bswap16_i32, { "r", "r" } },
{ INDEX_op_bswap32_i32, { "r", "r" } },
--
1.9.0
- [Qemu-devel] [PULL for-2.1 10/25] tcg-aarch64: Use CBZ and CBNZ, (continued)
- [Qemu-devel] [PULL for-2.1 10/25] tcg-aarch64: Use CBZ and CBNZ, Richard Henderson, 2014/04/16
- [Qemu-devel] [PULL for-2.1 11/25] tcg-aarch64: Reuse LR in translated code, Richard Henderson, 2014/04/16
- [Qemu-devel] [PULL for-2.1 12/25] tcg-aarch64: Introduce tcg_out_insn_3314, Richard Henderson, 2014/04/16
- [Qemu-devel] [PULL for-2.1 14/25] tcg-aarch64: Avoid add with zero in tlb load, Richard Henderson, 2014/04/16
- [Qemu-devel] [PULL for-2.1 09/25] tcg-aarch64: Create tcg_out_brcond, Richard Henderson, 2014/04/16
- [Qemu-devel] [PULL for-2.1 15/25] tcg-aarch64: Use tcg_out_call for qemu_ld/st, Richard Henderson, 2014/04/16
- [Qemu-devel] [PULL for-2.1 16/25] tcg-aarch64: Use ADR to pass the return address to the ld/st helpers, Richard Henderson, 2014/04/16
- [Qemu-devel] [PULL for-2.1 17/25] tcg-aarch64: Use TCGMemOp in qemu_ld/st, Richard Henderson, 2014/04/16
- [Qemu-devel] [PULL for-2.1 18/25] tcg-aarch64: Pass qemu_ld/st arguments directly, Richard Henderson, 2014/04/16
- [Qemu-devel] [PULL for-2.1 13/25] tcg-aarch64: Implement tcg_register_jit, Richard Henderson, 2014/04/16
- [Qemu-devel] [PULL for-2.1 20/25] tcg-aarch64: Support stores of zero,
Richard Henderson <=
- [Qemu-devel] [PULL for-2.1 19/25] tcg-aarch64: Implement TCG_TARGET_HAS_new_ldst, Richard Henderson, 2014/04/16
- [Qemu-devel] [PULL for-2.1 21/25] tcg-aarch64: Introduce tcg_out_insn_3507, Richard Henderson, 2014/04/16
- [Qemu-devel] [PULL for-2.1 22/25] tcg-aarch64: Merge aarch64_ldst_get_data/type into tcg_out_op, Richard Henderson, 2014/04/16
- [Qemu-devel] [PULL for-2.1 23/25] tcg-aarch64: Introduce tcg_out_insn_3312, _3310, _3313, Richard Henderson, 2014/04/16
- [Qemu-devel] [PULL for-2.1 24/25] tcg-aarch64: Prefer unsigned offsets before signed offsets for ldst, Richard Henderson, 2014/04/16
- [Qemu-devel] [PULL for-2.1 25/25] tcg-aarch64: Use tcg_out_mov in preference to tcg_out_movr, Richard Henderson, 2014/04/16
- Re: [Qemu-devel] [PULL for-2.1 00/25] tcg-aarch64 improvements, Peter Maydell, 2014/04/17