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[Qemu-devel] [PATCH v4 01/25] tcg-aarch64: Properly detect SIGSEGV write
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v4 01/25] tcg-aarch64: Properly detect SIGSEGV writes |
Date: |
Fri, 11 Apr 2014 08:40:03 -0700 |
Since the kernel doesn't pass any info on the reason for the fault,
disassemble the instruction to detect a store.
Signed-off-by: Richard Henderson <address@hidden>
---
user-exec.c | 29 +++++++++++++++++++++++------
1 file changed, 23 insertions(+), 6 deletions(-)
diff --git a/user-exec.c b/user-exec.c
index bc58056..c7106a6 100644
--- a/user-exec.c
+++ b/user-exec.c
@@ -465,16 +465,33 @@ int cpu_signal_handler(int host_signum, void *pinfo,
#elif defined(__aarch64__)
-int cpu_signal_handler(int host_signum, void *pinfo,
- void *puc)
+int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
{
siginfo_t *info = pinfo;
struct ucontext *uc = puc;
- uint64_t pc;
- int is_write = 0; /* XXX how to determine? */
+ uintptr_t pc = uc->uc_mcontext.pc;
+ uint32_t insn = *(uint32_t *)pc;
+ bool is_write;
- pc = uc->uc_mcontext.pc;
- return handle_cpu_signal(pc, (uint64_t)info->si_addr,
+ /* XXX: need kernel patch to get write flag faster. */
+ /* XXX: several of these could be combined. */
+ is_write = ( (insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */
+ || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */
+ || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */
+ || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */
+ || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */
+ || (insn & 0x3bc00000) == 0x28000000 /* C3.3.7 */
+ || (insn & 0x3be00c00) == 0x38000400 /* C3.3.8 */
+ || (insn & 0x3be00c00) == 0x38000c00 /* C3.3.9 */
+ || (insn & 0x3be00c00) == 0x38200800 /* C3.3.10 */
+ || (insn & 0x3be00c00) == 0x38000800 /* C3.3.11 */
+ || (insn & 0x3be00c00) == 0x38000000 /* C3.3.12 */
+ || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */
+ || (insn & 0x3bc00000) == 0x29000000 /* C3.3.14 */
+ || (insn & 0x3bc00000) == 0x28800000 /* C3.3.15 */
+ || (insn & 0x3bc00000) == 0x29800000); /* C3.3.16 */
+
+ return handle_cpu_signal(pc, (uintptr_t)info->si_addr,
is_write, &uc->uc_sigmask, puc);
}
--
1.9.0
- [Qemu-devel] [PATCH v4 00/25] tcg-aarch64 improvments, Richard Henderson, 2014/04/11
- [Qemu-devel] [PATCH v4 02/25] tcg-aarch64: Use intptr_t apropriately, Richard Henderson, 2014/04/11
- [Qemu-devel] [PATCH v4 03/25] tcg-aarch64: Use TCGType and TCGMemOp constants, Richard Henderson, 2014/04/11
- [Qemu-devel] [PATCH v4 04/25] tcg-aarch64: Use MOVN in tcg_out_movi, Richard Henderson, 2014/04/11
- [Qemu-devel] [PATCH v4 01/25] tcg-aarch64: Properly detect SIGSEGV writes,
Richard Henderson <=
- [Qemu-devel] [PATCH v4 05/25] tcg-aarch64: Use ORRI in tcg_out_movi, Richard Henderson, 2014/04/11
- [Qemu-devel] [PATCH v4 06/25] tcg-aarch64: Special case small constants in tcg_out_movi, Richard Henderson, 2014/04/11
- [Qemu-devel] [PATCH v4 07/25] tcg-aarch64: Use adrp in tcg_out_movi, Richard Henderson, 2014/04/11
- [Qemu-devel] [PATCH v4 08/25] tcg-aarch64: Use symbolic names for branches, Richard Henderson, 2014/04/11
- [Qemu-devel] [PATCH v4 09/25] tcg-aarch64: Create tcg_out_brcond, Richard Henderson, 2014/04/11
- [Qemu-devel] [PATCH v4 10/25] tcg-aarch64: Use CBZ and CBNZ, Richard Henderson, 2014/04/11
- [Qemu-devel] [PATCH v4 11/25] tcg-aarch64: Reuse LR in translated code, Richard Henderson, 2014/04/11
- [Qemu-devel] [PATCH v4 12/25] tcg-aarch64: Introduce tcg_out_insn_3314, Richard Henderson, 2014/04/11
- [Qemu-devel] [PATCH v4 13/25] tcg-aarch64: Implement tcg_register_jit, Richard Henderson, 2014/04/11
- [Qemu-devel] [PATCH v4 14/25] tcg-aarch64: Avoid add with zero in tlb load, Richard Henderson, 2014/04/11