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Re: [Qemu-devel] [PATCH microblaze v1 1/1] net: xilinx_axienet.c: Add ph
From: |
Beniamino Galvani |
Subject: |
Re: [Qemu-devel] [PATCH microblaze v1 1/1] net: xilinx_axienet.c: Add phy soft reset bit clearing |
Date: |
Wed, 9 Apr 2014 23:02:18 +0200 |
User-agent: |
Mutt/1.5.21 (2010-09-15) |
On Tue, Apr 08, 2014 at 06:52:39PM -0700, Peter Crosthwaite wrote:
> From: Nathan Rossi <address@hidden>
>
> Clear the BMCR Reset when writing to registers.
>
> Signed-off-by: Nathan Rossi <address@hidden>
> [ PC:
> * Trivial style fixes to commit message
> ]
> Signed-off-by: Peter Crosthwaite <address@hidden>
> ---
>
> hw/net/xilinx_axienet.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
> index 839d97c..0f485a0 100644
> --- a/hw/net/xilinx_axienet.c
> +++ b/hw/net/xilinx_axienet.c
> @@ -142,6 +142,9 @@ tdk_write(struct PHY *phy, unsigned int req, unsigned int
> data)
> phy->regs[regnum] = data;
> break;
> }
> +
> + /* Unconditionally clear regs[BMCR][BMCR_RESET] */
> + phy->regs[0] &= ~0x8000;
> }
>
> static void
> --
Reviewed-by: Beniamino Galvani <address@hidden>
Ideally we should also restore default values of registers after a
reset, but probably it is not required for the guest to operate
properly.
Beniamino