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[Qemu-devel] [PULL 2.0 11/15] target-ppc: Correct VSX Integer to FP Conv
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PULL 2.0 11/15] target-ppc: Correct VSX Integer to FP Conversion |
Date: |
Tue, 8 Apr 2014 11:31:50 +0200 |
From: Tom Musta <address@hidden>
This patch corrects the VSX integer to floating point conversion instructions
by using the endian correct accessors. The auxiliary "j" index used by the
existing macros is now obsolete and is removed. The JOFFSET preprocessor
macro is also obsolete and removed.
Signed-off-by: Tom Musta <address@hidden>
Tested-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/fpu_helper.c | 37 +++++++++++++------------------------
1 file changed, 13 insertions(+), 24 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index abba703..c6f484f 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2487,12 +2487,6 @@ VSX_CMP(xvcmpeqsp, 4, float32, VsrW(i), eq, 0)
VSX_CMP(xvcmpgesp, 4, float32, VsrW(i), le, 1)
VSX_CMP(xvcmpgtsp, 4, float32, VsrW(i), lt, 1)
-#if defined(HOST_WORDS_BIGENDIAN)
-#define JOFFSET 0
-#else
-#define JOFFSET 1
-#endif
-
/* VSX_CVT_FP_TO_FP - VSX floating point/floating point conversion
* op - instruction mnemonic
* nels - number of elements (1, 2 or 4)
@@ -2614,7 +2608,7 @@ VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32,
VsrW(i), VsrW(i), 0U)
* jdef - definition of the j index (i or 2*i)
* sfprf - set FPRF
*/
-#define VSX_CVT_INT_TO_FP(op, nels, stp, ttp, sfld, tfld, jdef, sfprf, r2sp) \
+#define VSX_CVT_INT_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf, r2sp) \
void helper_##op(CPUPPCState *env, uint32_t opcode) \
{ \
ppc_vsr_t xt, xb; \
@@ -2624,7 +2618,6 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)
\
getVSR(xT(opcode), &xt, env); \
\
for (i = 0; i < nels; i++) { \
- int j = jdef; \
xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status); \
if (r2sp) { \
xt.tfld = helper_frsp(env, xt.tfld); \
@@ -2638,22 +2631,18 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)
\
helper_float_check_status(env); \
}
-VSX_CVT_INT_TO_FP(xscvsxddp, 1, int64, float64, u64[j], f64[i], i, 1, 0)
-VSX_CVT_INT_TO_FP(xscvuxddp, 1, uint64, float64, u64[j], f64[i], i, 1, 0)
-VSX_CVT_INT_TO_FP(xscvsxdsp, 1, int64, float64, u64[j], f64[i], i, 1, 1)
-VSX_CVT_INT_TO_FP(xscvuxdsp, 1, uint64, float64, u64[j], f64[i], i, 1, 1)
-VSX_CVT_INT_TO_FP(xvcvsxddp, 2, int64, float64, u64[j], f64[i], i, 0, 0)
-VSX_CVT_INT_TO_FP(xvcvuxddp, 2, uint64, float64, u64[j], f64[i], i, 0, 0)
-VSX_CVT_INT_TO_FP(xvcvsxwdp, 2, int32, float64, u32[j], f64[i], \
- 2*i + JOFFSET, 0, 0)
-VSX_CVT_INT_TO_FP(xvcvuxwdp, 2, uint64, float64, u32[j], f64[i], \
- 2*i + JOFFSET, 0, 0)
-VSX_CVT_INT_TO_FP(xvcvsxdsp, 2, int64, float32, u64[i], f32[j], \
- 2*i + JOFFSET, 0, 0)
-VSX_CVT_INT_TO_FP(xvcvuxdsp, 2, uint64, float32, u64[i], f32[j], \
- 2*i + JOFFSET, 0, 0)
-VSX_CVT_INT_TO_FP(xvcvsxwsp, 4, int32, float32, u32[j], f32[i], i, 0, 0)
-VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, u32[j], f32[i], i, 0, 0)
+VSX_CVT_INT_TO_FP(xscvsxddp, 1, int64, float64, VsrD(0), VsrD(0), 1, 0)
+VSX_CVT_INT_TO_FP(xscvuxddp, 1, uint64, float64, VsrD(0), VsrD(0), 1, 0)
+VSX_CVT_INT_TO_FP(xscvsxdsp, 1, int64, float64, VsrD(0), VsrD(0), 1, 1)
+VSX_CVT_INT_TO_FP(xscvuxdsp, 1, uint64, float64, VsrD(0), VsrD(0), 1, 1)
+VSX_CVT_INT_TO_FP(xvcvsxddp, 2, int64, float64, VsrD(i), VsrD(i), 0, 0)
+VSX_CVT_INT_TO_FP(xvcvuxddp, 2, uint64, float64, VsrD(i), VsrD(i), 0, 0)
+VSX_CVT_INT_TO_FP(xvcvsxwdp, 2, int32, float64, VsrW(2*i), VsrD(i), 0, 0)
+VSX_CVT_INT_TO_FP(xvcvuxwdp, 2, uint64, float64, VsrW(2*i), VsrD(i), 0, 0)
+VSX_CVT_INT_TO_FP(xvcvsxdsp, 2, int64, float32, VsrD(i), VsrW(2*i), 0, 0)
+VSX_CVT_INT_TO_FP(xvcvuxdsp, 2, uint64, float32, VsrD(i), VsrW(2*i), 0, 0)
+VSX_CVT_INT_TO_FP(xvcvsxwsp, 4, int32, float32, VsrW(i), VsrW(i), 0, 0)
+VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, VsrW(i), VsrW(i), 0, 0)
/* For "use current rounding mode", define a value that will not be one of
* the existing rounding model enums.
--
1.8.1.4
- [Qemu-devel] [PULL 2.0 03/15] softfloat: Introduce float32_to_uint64_round_to_zero, (continued)
- [Qemu-devel] [PULL 2.0 03/15] softfloat: Introduce float32_to_uint64_round_to_zero, Alexander Graf, 2014/04/08
- [Qemu-devel] [PULL 2.0 06/15] target-ppc: Correct LE Host Inversion of Lower VSRs, Alexander Graf, 2014/04/08
- [Qemu-devel] [PULL 2.0 13/15] PPC: Only enter MSR_POW when no interrupts pending, Alexander Graf, 2014/04/08
- [Qemu-devel] [PULL 2.0 09/15] target-ppc: Correct VSX FP to FP Conversions, Alexander Graf, 2014/04/08
- [Qemu-devel] [PULL 2.0 12/15] PPC: Clean up DECR implementation, Alexander Graf, 2014/04/08
- [Qemu-devel] [PULL 2.0 07/15] target-ppc: Correct Simple VSR LE Host Inversions, Alexander Graf, 2014/04/08
- [Qemu-devel] [PULL 2.0 10/15] target-ppc: Correct VSX FP to Integer Conversion, Alexander Graf, 2014/04/08
- [Qemu-devel] [PULL 2.0 08/15] target-ppc: Correct VSX Scalar Compares, Alexander Graf, 2014/04/08
- [Qemu-devel] [PULL 2.0 15/15] PPC: Add l1 cache sizes for 970 and above systems, Alexander Graf, 2014/04/08
- [Qemu-devel] [PULL 2.0 14/15] ppce500_spin: Initialize struct properly, Alexander Graf, 2014/04/08
- [Qemu-devel] [PULL 2.0 11/15] target-ppc: Correct VSX Integer to FP Conversion,
Alexander Graf <=
- [Qemu-devel] [PULL 2.0 04/15] target-ppc: Bug: VSX Convert to Integer Should Truncate, Alexander Graf, 2014/04/08
- [Qemu-devel] [PULL 2.0 02/15] pseries: Update SLOF firmware image to qemu-slof-20140404, Alexander Graf, 2014/04/08
- Re: [Qemu-devel] [PULL 2.0 00/15] ppc patch queue 2014-04-08 for 2.0, Peter Maydell, 2014/04/08