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[Qemu-devel] [PATCH 05/26] tcg-aarch64: Use ORRI in tcg_out_movi
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 05/26] tcg-aarch64: Use ORRI in tcg_out_movi |
Date: |
Fri, 14 Mar 2014 19:48:31 -0700 |
The subset of logical immediates that we support is quite quick to test,
and such constants are quite common to want to load.
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/aarch64/tcg-target.c | 70 +++++++++++++++++++++++++++---------------------
1 file changed, 39 insertions(+), 31 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index a7b6796..0f23e43 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -527,6 +527,37 @@ static void tcg_out_movr_sp(TCGContext *s, TCGType ext,
TCGReg rd, TCGReg rn)
tcg_out_insn(s, 3401, ADDI, ext, rd, rn, 0);
}
+/* This function is used for the Logical (immediate) instruction group.
+ The value of LIMM must satisfy IS_LIMM. See the comment above about
+ only supporting simplified logical immediates. */
+static void tcg_out_logicali(TCGContext *s, AArch64Insn insn, TCGType ext,
+ TCGReg rd, TCGReg rn, uint64_t limm)
+{
+ unsigned h, l, r, c;
+
+ assert(is_limm(limm));
+
+ h = clz64(limm);
+ l = ctz64(limm);
+ if (l == 0) {
+ r = 0; /* form 0....01....1 */
+ c = ctz64(~limm) - 1;
+ if (h == 0) {
+ r = clz64(~limm); /* form 1..10..01..1 */
+ c += r;
+ }
+ } else {
+ r = 64 - l; /* form 1....10....0 or 0..01..10..0 */
+ c = r - h - 1;
+ }
+ if (ext == TCG_TYPE_I32) {
+ r &= 31;
+ c &= 31;
+ }
+
+ tcg_out_insn_3404(s, insn, ext, rd, rn, ext, r, c);
+}
+
static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
tcg_target_long value)
{
@@ -546,6 +577,14 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
TCGReg rd,
}
ivalue = ~svalue;
+ /* Check for bitfield immediates. For the benefit of 32-bit quantities,
+ use the sign-extended value. That lets us match rotated values such
+ as 0xff0000ff with the same 64-bit logic matching 0xffffffffff0000ff. */
+ if (is_limm(svalue)) {
+ tcg_out_logicali(s, I3404_ORRI, type, rd, TCG_REG_XZR, svalue);
+ return;
+ }
+
/* Would it take fewer insns to begin with MOVN? For the value and its
inverse, count the number of 16-bit lanes that are 0. */
for (i = wantinv = imask = 0; i < (32 << type); i += 16) {
@@ -890,37 +929,6 @@ static void tcg_out_addsubi(TCGContext *s, int ext, TCGReg
rd,
}
}
-/* This function is used for the Logical (immediate) instruction group.
- The value of LIMM must satisfy IS_LIMM. See the comment above about
- only supporting simplified logical immediates. */
-static void tcg_out_logicali(TCGContext *s, AArch64Insn insn, TCGType ext,
- TCGReg rd, TCGReg rn, uint64_t limm)
-{
- unsigned h, l, r, c;
-
- assert(is_limm(limm));
-
- h = clz64(limm);
- l = ctz64(limm);
- if (l == 0) {
- r = 0; /* form 0....01....1 */
- c = ctz64(~limm) - 1;
- if (h == 0) {
- r = clz64(~limm); /* form 1..10..01..1 */
- c += r;
- }
- } else {
- r = 64 - l; /* form 1....10....0 or 0..01..10..0 */
- c = r - h - 1;
- }
- if (ext == TCG_TYPE_I32) {
- r &= 31;
- c &= 31;
- }
-
- tcg_out_insn_3404(s, insn, ext, rd, rn, ext, r, c);
-}
-
static inline void tcg_out_addsub2(TCGContext *s, int ext, TCGReg rl,
TCGReg rh, TCGReg al, TCGReg ah,
tcg_target_long bl, tcg_target_long bh,
--
1.8.5.3
- [Qemu-devel] [PATCH 03/26] tcg-aarch64: Use TCGType and TCGMemOp constants, (continued)
- [Qemu-devel] [PATCH 03/26] tcg-aarch64: Use TCGType and TCGMemOp constants, Richard Henderson, 2014/03/14
- [Qemu-devel] [PATCH 04/26] tcg-aarch64: Use MOVN in tcg_out_movi, Richard Henderson, 2014/03/14
- [Qemu-devel] [PATCH 06/26] tcg-aarch64: Special case small constants in tcg_out_movi, Richard Henderson, 2014/03/14
- [Qemu-devel] [PATCH 07/26] tcg-aarch64: Use adrp in tcg_out_movi, Richard Henderson, 2014/03/14
- [Qemu-devel] [PATCH 05/26] tcg-aarch64: Use ORRI in tcg_out_movi,
Richard Henderson <=
- [Qemu-devel] [PATCH 08/26] tcg-aarch64: Use symbolic names for branches, Richard Henderson, 2014/03/14
- [Qemu-devel] [PATCH 09/26] tcg-aarch64: Create tcg_out_brcond, Richard Henderson, 2014/03/14
- [Qemu-devel] [PATCH 10/26] tcg-aarch64: Use CBZ and CBNZ, Richard Henderson, 2014/03/14
- [Qemu-devel] [PATCH 11/26] tcg-aarch64: Reuse FP and LR in translated code, Richard Henderson, 2014/03/14