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[Qemu-devel] [PULL 07/14] tcg-aarch64: Support andc, orc, eqv, not, neg
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 07/14] tcg-aarch64: Support andc, orc, eqv, not, neg |
Date: |
Fri, 14 Mar 2014 13:09:44 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Claudio Fontana <address@hidden>
Tested-by: Claudio Fontana <address@hidden>
---
tcg/aarch64/tcg-target.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++++
tcg/aarch64/tcg-target.h | 20 ++++++++---------
2 files changed, 67 insertions(+), 10 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 9a34a15..5850ae4 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -284,8 +284,11 @@ typedef enum {
/* Logical shifted register instructions (without a shift). */
I3510_AND = 0x0a000000,
+ I3510_BIC = 0x0a200000,
I3510_ORR = 0x2a000000,
+ I3510_ORN = 0x2a200000,
I3510_EOR = 0x4a000000,
+ I3510_EON = 0x4a200000,
I3510_ANDS = 0x6a000000,
} AArch64Insn;
@@ -1226,6 +1229,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
+ case INDEX_op_neg_i64:
+ case INDEX_op_neg_i32:
+ tcg_out_insn(s, 3502, SUB, ext, a0, TCG_REG_XZR, a1);
+ break;
+
case INDEX_op_and_i32:
a2 = (int32_t)a2;
/* FALLTHRU */
@@ -1237,6 +1245,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
+ case INDEX_op_andc_i32:
+ a2 = (int32_t)a2;
+ /* FALLTHRU */
+ case INDEX_op_andc_i64:
+ if (c2) {
+ tcg_out_logicali(s, I3404_ANDI, ext, a0, a1, ~a2);
+ } else {
+ tcg_out_insn(s, 3510, BIC, ext, a0, a1, a2);
+ }
+ break;
+
case INDEX_op_or_i32:
a2 = (int32_t)a2;
/* FALLTHRU */
@@ -1248,6 +1267,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
+ case INDEX_op_orc_i32:
+ a2 = (int32_t)a2;
+ /* FALLTHRU */
+ case INDEX_op_orc_i64:
+ if (c2) {
+ tcg_out_logicali(s, I3404_ORRI, ext, a0, a1, ~a2);
+ } else {
+ tcg_out_insn(s, 3510, ORN, ext, a0, a1, a2);
+ }
+ break;
+
case INDEX_op_xor_i32:
a2 = (int32_t)a2;
/* FALLTHRU */
@@ -1259,6 +1289,22 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
+ case INDEX_op_eqv_i32:
+ a2 = (int32_t)a2;
+ /* FALLTHRU */
+ case INDEX_op_eqv_i64:
+ if (c2) {
+ tcg_out_logicali(s, I3404_EORI, ext, a0, a1, ~a2);
+ } else {
+ tcg_out_insn(s, 3510, EON, ext, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_not_i64:
+ case INDEX_op_not_i32:
+ tcg_out_insn(s, 3510, ORN, ext, a0, TCG_REG_XZR, a1);
+ break;
+
case INDEX_op_mul_i64:
case INDEX_op_mul_i32:
tcg_out_mul(s, ext, a0, a1, a2);
@@ -1455,6 +1501,17 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_or_i64, { "r", "r", "rL" } },
{ INDEX_op_xor_i32, { "r", "r", "rwL" } },
{ INDEX_op_xor_i64, { "r", "r", "rL" } },
+ { INDEX_op_andc_i32, { "r", "r", "rwL" } },
+ { INDEX_op_andc_i64, { "r", "r", "rL" } },
+ { INDEX_op_orc_i32, { "r", "r", "rwL" } },
+ { INDEX_op_orc_i64, { "r", "r", "rL" } },
+ { INDEX_op_eqv_i32, { "r", "r", "rwL" } },
+ { INDEX_op_eqv_i64, { "r", "r", "rL" } },
+
+ { INDEX_op_neg_i32, { "r", "r" } },
+ { INDEX_op_neg_i64, { "r", "r" } },
+ { INDEX_op_not_i32, { "r", "r" } },
+ { INDEX_op_not_i64, { "r", "r" } },
{ INDEX_op_shl_i32, { "r", "r", "ri" } },
{ INDEX_op_shr_i32, { "r", "r", "ri" } },
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 82ad919..f2945b5 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -47,12 +47,12 @@ typedef enum {
#define TCG_TARGET_HAS_ext16u_i32 1
#define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1
-#define TCG_TARGET_HAS_not_i32 0
-#define TCG_TARGET_HAS_neg_i32 0
+#define TCG_TARGET_HAS_not_i32 1
+#define TCG_TARGET_HAS_neg_i32 1
#define TCG_TARGET_HAS_rot_i32 1
-#define TCG_TARGET_HAS_andc_i32 0
-#define TCG_TARGET_HAS_orc_i32 0
-#define TCG_TARGET_HAS_eqv_i32 0
+#define TCG_TARGET_HAS_andc_i32 1
+#define TCG_TARGET_HAS_orc_i32 1
+#define TCG_TARGET_HAS_eqv_i32 1
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0
#define TCG_TARGET_HAS_deposit_i32 0
@@ -75,12 +75,12 @@ typedef enum {
#define TCG_TARGET_HAS_bswap16_i64 1
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
-#define TCG_TARGET_HAS_not_i64 0
-#define TCG_TARGET_HAS_neg_i64 0
+#define TCG_TARGET_HAS_not_i64 1
+#define TCG_TARGET_HAS_neg_i64 1
#define TCG_TARGET_HAS_rot_i64 1
-#define TCG_TARGET_HAS_andc_i64 0
-#define TCG_TARGET_HAS_orc_i64 0
-#define TCG_TARGET_HAS_eqv_i64 0
+#define TCG_TARGET_HAS_andc_i64 1
+#define TCG_TARGET_HAS_orc_i64 1
+#define TCG_TARGET_HAS_eqv_i64 1
#define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 0
#define TCG_TARGET_HAS_deposit_i64 0
--
1.8.5.3
- [Qemu-devel] [PULL 00/14] tcg/aarch64 improvements, part 2, Richard Henderson, 2014/03/14
- [Qemu-devel] [PULL 01/14] tcg-aarch64: Introduce tcg_out_insn, Richard Henderson, 2014/03/14
- [Qemu-devel] [PULL 02/14] tcg-aarch64: Convert shift insns to tcg_out_insn, Richard Henderson, 2014/03/14
- [Qemu-devel] [PULL 04/14] tcg-aarch64: Implement mov with tcg_out_insn, Richard Henderson, 2014/03/14
- [Qemu-devel] [PULL 03/14] tcg-aarch64: Introduce tcg_out_insn_3401, Richard Henderson, 2014/03/14
- [Qemu-devel] [PULL 05/14] tcg-aarch64: Handle constant operands to add, sub, and compare, Richard Henderson, 2014/03/14
- [Qemu-devel] [PULL 06/14] tcg-aarch64: Handle constant operands to and, or, xor, Richard Henderson, 2014/03/14
- [Qemu-devel] [PULL 07/14] tcg-aarch64: Support andc, orc, eqv, not, neg,
Richard Henderson <=
- [Qemu-devel] [PULL 08/14] tcg-aarch64: Support movcond, Richard Henderson, 2014/03/14
- [Qemu-devel] [PULL 09/14] tcg-aarch64: Use tcg_out_insn for setcond, Richard Henderson, 2014/03/14
- [Qemu-devel] [PULL 10/14] tcg-aarch64: Support deposit, Richard Henderson, 2014/03/14
- [Qemu-devel] [PULL 11/14] tcg-aarch64: Support add2, sub2, Richard Henderson, 2014/03/14
- [Qemu-devel] [PULL 12/14] tcg-aarch64: Support muluh, mulsh, Richard Henderson, 2014/03/14
- [Qemu-devel] [PULL 13/14] tcg-aarch64: Support div, rem, Richard Henderson, 2014/03/14
- [Qemu-devel] [PULL 14/14] tcg-aarch64: Introduce tcg_out_insn_3405, Richard Henderson, 2014/03/14
- Re: [Qemu-devel] [PULL 00/14] tcg/aarch64 improvements, part 2, Peter Maydell, 2014/03/15