[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Qemu-devel] [PATCH v2 1/4] pl011: reset the fifo when enabled or disabl

From: Rob Herring
Subject: [Qemu-devel] [PATCH v2 1/4] pl011: reset the fifo when enabled or disabled
Date: Fri, 14 Mar 2014 13:22:28 -0500

From: Rob Herring <address@hidden>

Intermittent issues have been seen where no serial input occurs. It
appears the pl011 gets in a state where the rx interrupt never fires
because the rx interrupt only asserts when crossing the fifo trigger
level. The fifo state appears to get out of sync when the pl011 is
re-configured. This combined with the rx timeout interrupt not being
modeled results in no more rx interrupts.

Disabling the fifo is the recommended way to clear the tx fifo in the
TRM (section 3.3.8). The behavior in this case for the rx fifo is
undefined in the TRM, but having fifo contents to be maintained during
configuration changes is not likely expected behavior. Reseting the
fifo state when the fifo size is changed is the simplest solution.

Signed-off-by: Rob Herring <address@hidden>
 hw/char/pl011.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index a8ae6f4..f0c3fa3 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -162,6 +162,10 @@ static void pl011_write(void *opaque, hwaddr offset,
         s->fbrd = value;
     case 11: /* UARTLCR_H */
+        if (!((s->lcr ^ value) & 0x10)) {
+            s->read_count = 0;
+            s->read_pos = 0;
+        }
         s->lcr = value;

reply via email to

[Prev in Thread] Current Thread [Next in Thread]